Peripheral emulation apparatus

Claim 2

In a data processing system having a first processor generating address and data signals, at least one peripheral unit having a plurality of registers for storing parameter data which controls the operation of said peripheral unit, at least selected ones of said registers being device specific registers, and means responsive to said address and said data signals for transferring said parameter data from said first processor to said registers, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit, said apparatus comprising means responsive to said address and said data signals for generating a flag signal when said parameter data is being transferred from said first processor to said device specific registers; means responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit; and means responsive to said address and data signals for providing and writing alternate parameter data into said device specific registers.

Claim 3

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 1 wherein said providing and writing means comprises a second processor.

Claim 4

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 2 wherein said generating means includes means responsive to said data signals for alerting said second processor that said first processor has attempted or will attempt to access said device specific registers, said second processor thereupon generating said flag signal.

Claim 5

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 3 wherein said peripheral unit requires an enable signal to operate and said generating means further includes means responsive to said data signals for preventing said first processor from forwarding an enable signal to said peripheral unit.

Claim 6

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 2 wherein said disconnecting means includes a plurality of gate means responsive to said flag signal for disconnecting said first processor from said peripheral unit and for connecting said second processor to said peripheral unit.

Claim 7

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 1 including a mode register for storing mode parameters which control the operation of said data processing system, and wherein said second processor includes means for examining the contents of said mode register to determine whether said first processor has attempted to access said device specific registers.

Claim 8

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 1 wherein said peripheral unit includes second registers for storing data affecting non-device specific operations of said peripheral unit and said apparatus further includes logic means which enables said first processor to access said second registers.

Claim 9

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 7, including a mode register for storing mode parameters which control the operation of said data processing system, and wherein said flag generating means includes means responsive to a change in the contents of said mode register for alerting said second processor that said first processor has attempted or will attempt to access said device specific registers.

Claim 10

In a data processing system having a first processor generating address, data and an enable signal, at least one peripheral unit having a plurality of registers for storing device-specific parameter data which controls the operation of said peripheral unit, a data bus connecting said processor and said registers for transferring said parameter data from said first processor to said registers, and means responsive to said enable signal for causing parameter data on said data bus to be written into said registers, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit, said apparatus comprising, a second processor, means responsive to changes in selected ones of said data signals for alerting said second processor that said first processor has attempted or will attempt to write parameter data into said registers, said second processor thereupon generating a flag signal, first gate means connected in said data bus between said first processor and said peripheral unit and responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit, and means responsive to said address and data signals for generating an alternative enable signal and for writing alternate parameter data from said second processor into said registers.

Claim 11

In a data processing system having a first processor generating address, data and an enable signal, at least one peripheral unit having a plurality of registers for storing device-specific parameter data which controls the operation of said peripheral unit, a data bus connecting said processor and said registers for transferring said parameter data from said first processor to said registers, and means responsive to said enable signal for causing parameter data on said data bus to be written into said registers, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit, said apparatus comprising, a second processor, means responsive to changes in selected ones of said data signals for alerting said second processor that said first processor has attempted or will attempt to write parameter data into said registers, said second processor thereupon generating a flag signal, first gate means connected in said data bus between said first processor and said peripheral unit and responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit, and means responsive to said address and data signals for generating an alternative enable signal and for writing alternate parameter data from said second processor into said registers.

Claim 12

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 9, including a mode register for storing mode parameters which control the operation of said data processing system, and wherein said second processor includes means for examining the contents of said mode register to determine whether said first processor is attempting to access said registers.

Claim 13

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 10 wherein said peripheral unit includes additional registers for storing data affecting non-device specific operations of said peripheral unit and said apparatus further includes logic means which enables said first processor to access said additional registers.

Claim 14

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 10 wherein said alerting means includes means responsive to a change in the contents of said mode register for alerting said second processor that said first processor has attempted or will attempt to access said registers.

Claim 15

In a data processing system, apparatus for allowing a software program written for use with a different peripheral unit to operate with said peripheral unit according to claim 9 further comprising second gate means connected between said first processor and said peripheral unit and responsive to said data signals for temporarily disconnecting said enable signal from said peripheral unit.

Claim 16

A data processing system comprising, a first processor having means for generating address signals, data signals and control signals, at least one peripheral unit having a plurality of registers for storing device-specific parameter data which controls the operation of said peripheral unit, a data bus connecting said first processor and said registers for transferring said parameter data from said first processor to said registers, means responsive to one of said control signals generated by said first processor for enabling parameter data on said data bus to be written into said registers, a mode register for storing parameters which control the operation of said data processing system, a second processor having means for generating data and control signals, means responsive to changes in mode signals stored in said mode register for alerting said second processor that said first processor has attempted or will attempt to write parameter data into said registers, said second processor thereupon generating a flag signal, first gate means connected in said data bus between said first processor and said peripheral unit and responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit, and a multiplexer, responsive to said flag signal for disconnecting the control signals generated by said first processor from said peripheral unit and for connecting data and control signals generated by said second processor to said peripheral unit, said second processor thereupon writing alternate parameter data into said registers.

Claim 17

A data processing system comprising, a first processor having means for generating address signals, data signals and control signals, at least one peripheral unit having a plurality of registers for storing device-specific parameter data which controls the operation of said peripheral unit, a data bus connecting said first processor and said registers for transferring said parameter data from said first processor to said registers, means responsive to one of said control signals generated by said first processor for enabling parameter data on said data bus to be written into said registers, a mode register for storing parameters which control the operation of said data processing system, a second processor having means for generating data and control signals, means responsive to changes in mode signals stored in said mode register for alerting said second processor that said first processor has attempted or will attempt to write parameter data into said registers, said second processor thereupon generating a flag signal, first gate means connected in said data bus between said first processor and said peripheral unit and responsive to said flag signal for temporarily disconnecting said first processor from said peripheral unit, and a multiplexer, responsive to said flag signal for disconnecting the control signals generated by said first processor from said peripheral unit and for connecting data and control signals generated by said second processor to said peripheral unit, said second processor thereupon writing alternate parameter data into said registers.

Claim 18

A data processing system, according to claim 14 wherein said peripheral unit includes additional registers for storing data affecting non-device specific operations of said peripheral device and said second processor does not generate said flag signal when said first processor accesses said additional registers.

Claim 19

A data processing system according to claim 15 further comprising an address decoder responsive to said address signals generated by said first processor for generating an enable signal for enabling operation of said peripheral unit, said enable signal passing through said multiplexer.

Claim 20

A data processing system according to claim 16 further comprising means responsive to said enable signal and to predetermined data patterns on said data bus for disconnecting said enable signal from said multiplexer so that said first processor can only access predetermined registers in said peripheral device.

Claim 21

A data processing system according to claim 17 wherein said alerting means comprises means for generating a pulse signal each time a change occurs in said mode register contents and means responsive to said pulse signal for generating an interrupt signal and for providing said interrupt signal to said second processor.

Claim 22

A data processing system according to claim 17 wherein said second processor comprises means responsive to said interrupt signal for examining the contents of said mode register to determine if said first processor has attempted or will attempt to access registers containing device-specific parameters.