Patent US2585557A successfully refreshed from Google Patents.
US4800523A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device interface controller having device specific and device common instructions separately stored
Assignee: Alcatel Lucent NV
•
Filing: 1988-02-16
•
Granted: 1989-01-24
•
Expires: 2008-02-16
Abstract
Abstract An apparatus for controlling a plurality of peripherals attached to a common high speed parallel bus, includes a first program therein, which program includes a fixed set of generalized command and control instructions and a device specific program therein, which device specific program includes command and control instructions for a plurality of different devices.
Inventors
- 👤 Eugene P. Gerety
- 👤 Jitender K. Vij
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 17:54
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F13/20; G06F13/22; G06F13/38; G06F13/382; G06F13/385
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
279 words
A device interface controller, for use in a data transport controller which includes a storage medium for temporarily storing data transmitted from an external source, and a microcomputer for controlling transport of the transmitted data through the storage medium to any selected one of a plurality of data communication devices interconnected to the data transport controller through a device bus, said device interface controller comprising: device bus interface means for interfacing with said device bus interconnected with said plurality of data communication devices; interfacing means including microcomputer interfacing means for interfacing with said microcomputer and storage medium interfacing means for interfacing with said storage medium of said data transport controller; instruction storing means separate from said storage medium, which includes common instruction storing means, for storing instructions for performing a data transfer operation which are common to all of said plurality of data communication devices, and specific instruction storing means, for storing instructions for performing a data transfer operation which are specific to each respective one of said plurality of data communication devices, including a selected one of the data communication devices; and a dedicated microprocessor responsive to said microcomputer through said microcomputer interfacing means for controlling data transport between said storage medium interfacing means with said storage medium and said bus device interface means with said plurality of data communication devices, wherein said dedicated microprocessor executes, for a data transport operation to the selected one of said data communication devices, common device instructions from said common instruction storing means which are common to all of said data communication devices, and specific device instructions from said specific instruction storing means which are specific to the selected data communication device.
Claim 2
Independent Claim
279 words
A device interface controller, for use in a data transport controller which includes a storage medium for temporarily storing data transmitted from an external source, and a microcomputer for controlling transport of the transmitted data through the storage medium to any selected one of a plurality of data communication devices interconnected to the data transport controller through a device bus, said device interface controller comprising: device bus interface means for interfacing with said device bus interconnected with said plurality of data communication devices; interfacing means including microcomputer interfacing means for interfacing with said microcomputer and storage medium interfacing means for interfacing with said storage medium of said data transport controller; instruction storing means separate from said storage medium, which includes common instruction storing means, for storing instructions for performing a data transfer operation which are common to all of said plurality of data communication devices, and specific instruction storing means, for storing instructions for performing a data transfer operation which are specific to each respective one of said plurality of data communication devices, including a selected one of the data communication devices; and a dedicated microprocessor responsive to said microcomputer through said microcomputer interfacing means for controlling data transport between said storage medium interfacing means with said storage medium and said bus device interface means with said plurality of data communication devices, wherein said dedicated microprocessor executes, for a data transport operation to the selected one of said data communication devices, common device instructions from said common instruction storing means which are common to all of said data communication devices, and specific device instructions from said specific instruction storing means which are specific to the selected data communication device.
Claim 3
Dependent Claim
54 words
Device interface as claimed in claim 1, wherein said microprocessor includes: an arithmetic logic unit; and a microprogram controller, said arithmetic logic unit and said microprogram controller having a scratch pad memory associated therewith, whereby data manipulation can be performed on data transferred between said device bus interface and said storage medium interface means.
Claim 4
Dependent Claim
46 words
Device interface controller as claimed in claim 2 wherein said instruction storage means includes a plurality of programmable read-only-memory devices; an address/data bus, and means for regulating access by said microprogram controller to said address/data bus and the output of said plurality of programmable read-only-memory devices.
Claim 5
Dependent Claim
64 words
Device interface controller as claimed in claim 3 wherein said access regulating means includes; first tri-state buffer serially connected in said address/data bus between said storage medium and said microprogram controller; a second tri-state buffer serially connected in the path from said output of said programmable read-only-memory and said microprogram controller; and means for exclusively enabling either said first or said second tri-state buffer.
Claim 6
Dependent Claim
31 words
Device interface controller as claimed in claim 4 wherein said exclusive enabling means is a binary inverter, said binary inverter being positioned serially between said first and said second tri-state buffers.
Claim 7
Dependent Claim
18 words
Device interface controller as claimed in claim 5 wherein said storage medium interfacing means includes an address/data bus.
Claim 8
Dependent Claim
26 words
Device interface controller as claimed in claim 1 wherein said storing means includes instructions only for said data communication devices operating under the same communication protocol.
Claim 9
Dependent Claim
20 words
Device interface controller as claimed in claim 1 wherein said instruction storage means is a plurality of programmable read-only-memory devices.
Claim 10
Dependent Claim
38 words
Device interface controller as claimed in claim 1 wherein said microcomputer interfacing means directly interfaces with and is limited to the receipt of channel attention signals from said microcomputer and generation of interrupt request signals from said controller.
Claim 11
Dependent Claim
18 words
Device interface controller as claimed in claim 9 wherein said direct microcomputer interface means includes a first flip-flop.
Claim 12
Dependent Claim
16 words
Device interface controller as claimed in claim 10 further comprising: means for monitoring said device bus.
Claim 13
Dependent Claim
18 words
Device interface controller as claimed in claim 11 wherein said device bus monitoring means is a second flip-flop.
Claim 14
Dependent Claim
28 words
Device interface controller as claimed in claim 12 further comprising: means for interfacing said direct microcomputer interface means and said device bus monitoring means with said dedicated microprocessor.
References Cited (Backward Citations)
US4115852A
Cited
US4156932A
Cited
US4321665A
Cited
US4371932A
Cited
US4452136A
Cited
US4485439A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-01-24 | 1992-07-25 | 1993-01-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-01-24 | 1996-07-25 | 1997-01-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-01-24 | 2000-07-25 | 2001-01-24 | $7700.00 | Window Closed / Lapsed |