Patent US4871929A successfully refreshed from Google Patents.
US4871929A
Expired / Lapsed
US
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ECL logic gate
Assignee: Semiconductor Components Industries LLC
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Filing: 1988-07-07
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Granted: 1989-10-03
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Expires: 2008-07-07
Abstract
Abstract An ECL logic gate includes an input stage, an output stage, and a multifunction current mirror circuit. The input stage includes a plurality of input transistors, a reference transistor, and an output which indicates the relative conductivities of said reference transistor as compared to one or more of the input transistors. This output is coupled to the output stage. A current mirror circuit having first and second current paths is provided in which the input stage is coupled in series with the first current path, and the output stage is coupled in series with the second current path.
Inventors
- 👤 Roger L. Hollstein
- 👤 M. Ngheim Phan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 19:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0008; H03K19/001
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
79 words
A logic gate, comprising: an input stage having a plurality of inputs and a first output; an output stage coupled to said first output; and current mirror means having first and second current paths for producing in said first current path a current which is a function of the current flowing in said second current path, said input stage coupled in series with said first current path, and said output stage coupled in series with said second current path.
Claim 2
Dependent Claim
79 words
A logic gate, comprising: an input stage having a plurality of inputs and a first output; an output stage coupled to said first output; and current mirror means having first and second current paths for producing in said first current path a current which is a function of the current flowing in said second current path, said input stage coupled in series with said first current path, and said output stage coupled in series with said second current path.
Claim 3
Dependent Claim
158 words
A logic gate, comprising: an input stage having a plurality of inputs and a first output; an output stage coupled to said first output; and current mirror means having first and second current paths for producing in said first current path a current which is a function of the current flowing in said second current path said input stage coupled in series with said first current path, and said output stage coupled in series with said second current path; wherein said output stage includes, (a) a first transistor having a base coupled to said first output, a collector coupled to a first power supply terminal, and having an emitter; (b) a second transistor having a base coupled to a first reference voltage terminal, a collector coupled to said emitter of said first transistor, and having an emitter; and (c) resistor means coupled between said emitter of said second transistor and second current path of said current mirror means.
Claim 4
Dependent Claim
158 words
A logic gate, comprising: an input stage having a plurality of inputs and a first output; an output stage coupled to said first output; and current mirror means having first and second current paths for producing in said first current path a current which is a function of the current flowing in said second current path said input stage coupled in series with said first current path, and said output stage coupled in series with said second current path; wherein said output stage includes, (a) a first transistor having a base coupled to said first output, a collector coupled to a first power supply terminal, and having an emitter; (b) a second transistor having a base coupled to a first reference voltage terminal, a collector coupled to said emitter of said first transistor, and having an emitter; and (c) resistor means coupled between said emitter of said second transistor and second current path of said current mirror means.
Claim 5
Dependent Claim
69 words
A logic gate according to claim 2 wherein said current mirror means comprises: a third transistor having a collector coupled to said input stage, an emitter coupled to a second supply voltage terminal and having a base; and diode means having a first terminal coupled to the base of said third transistor and to said resistor means and having a second terminal coupled to said second supply voltage terminal.
Claim 6
Dependent Claim
43 words
A logic gate according to claim 3 wherein said diode means comprises a fourth transistor having base and collector terminals coupled to the base of said third transistor and said resistor means and having an emitter coupled to said second supply voltage terminal.
Claim 7
Dependent Claim
114 words
A logic gate according to claim 3 wherein said input stage comprises: a reference transistor having a base coupled to a second reference voltage terminal, an emitter coupled to the collector of said third transistor and having a collector; at least first and second input transistors each having an emitter coupled to the collector of said third transistor, a base coupled to one of first and second input terminals, and each having a collector; a second resistive means coupled between said first supply voltage terminal and the collectors of said first and second input transistors; and a third resistive means coupled between said first supply voltage terminal and the collector of said reference transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-10-02 | 1993-04-03 | 1993-10-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-10-02 | 1997-04-03 | 1997-10-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-10-02 | 2001-04-03 | 2001-10-03 | $7700.00 | Window Closed / Lapsed |