US4870028A
Expired / Lapsed
US
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Method of making double gate static induction thyristor
Assignee: Mitsubishi Electric Corp
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Filing: 1989-03-12
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Granted: 1989-09-28
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Expires: 2009-03-12
Abstract
Abstract A double gate static induction thyristor comprises an n - semiconductor substrate having first and second principal surfaces opposite to each other. An n - epitaxial semiconductor layer is formed on the first principal surface of the substrate, and a p - epitaxial semiconductor layer is formed on the second principal surface of the substrate. A cathode electrode is deposited on the surface of the n - epitaxial layer, and an anode electrode is deposited on the surface of the p - epitaxial layer. In addition, a first gate electrode is formed on the first principal surface of the substrate, and a second gate electrode is formed on the second principal surface of the substrate.
Inventors
- 👤 Jun-ichi Nishizawa
- 👤 Hisao Kondoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 20:50
CPC Classifications
H; H10; H10D; H10D12/00; H10D12/211; H10D12/212; H10D62/00; H10D62/10; H10D62/17; H10D62/343
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
117 words
A method for manufacturing a double gate static induction thyristor comprising the steps of: preparing a semiconductor substrate of a first conduction type having first and second principal surfaces opposite to each other; selectively forming a first epitaxial layer of the first conductor type on the first principal surface of the substrate; selectively forming a second epitaxial layer of a second conduction type opposite to the first conduction type, on the second principal surface of the substrate; and forming electrodes on the first and second principal surfaces and the surface of the first and second epitaxial layers so as to provide a first gate electrode, a second gate electrode, a cathode electrode and an anode electrode, respectively.
Claim 2
Independent Claim
117 words
A method for manufacturing a double gate static induction thyristor comprising the steps of: preparing a semiconductor substrate of a first conduction type having first and second principal surfaces opposite to each other; selectively forming a first epitaxial layer of the first conductor type on the first principal surface of the substrate; selectively forming a second epitaxial layer of a second conduction type opposite to the first conduction type, on the second principal surface of the substrate; and forming electrodes on the first and second principal surfaces and the surface of the first and second epitaxial layers so as to provide a first gate electrode, a second gate electrode, a cathode electrode and an anode electrode, respectively.
Claim 3
Dependent Claim
66 words
A method as claimed in claim 1 wherein the first epitaxial layer is formed by the steps of depositing a first semiconductor layer of the first conduction type on the first principal surface of the substrate by means of an epitaxial growth process, and selectively removing the first epitaxial layer by an etching process to cause a portion of the first principal surface to be exposed.
Claim 4
Dependent Claim
66 words
A method as claimed in claim 1 wherein the second epitaxial layer is formed by the steps of depositing a second semiconductor layer of the second conduction type on the second principal surface of the substrate by means of an epitaxial growth process, and selectively removing the second epitaxial layer by an etching process to cause a portion of the second principal surface to be exposed.
Claim 5
Dependent Claim
54 words
A method as claimed in claim 1 wherein before formation of the firs and second epitaxial layers, first and second gate regions are selectively formed in the first and second principal surfaces of the substrate, respectively, and wherein the first and second gate electrodes are deposited on the first and second gate regions, respectively.
Claim 6
Dependent Claim
63 words
A method as claimed in claim 4 wherein the first epitaxial layer is formed by the steps of depositing a first semiconductor layer of the first conduction type on the first principal surface of the substrate by means of an epitaxial growth process, and selectively removing the first epitaxial layer by an etching process to cause the first gate region to be exposed.
Claim 7
Dependent Claim
63 words
A method as claimed in claim 4 wherein the second epitaxial layer is formed by the steps of depositing a second semiconductor layer of the second conduction type on the second principal surface of the substrate by means of an epitaxial growth process, and selectively removing the second epitaxial layer by an etching process to cause the second gate region to be exposed.
Claim 8
Dependent Claim
51 words
A method as claimed in claim 1 wherein the surfaces of the first and second epitaxial layers are strongly doped by impurities of the first and second conduction types, respectively, and the cathode and anode electrodes are deposited on the strongly doped surfaces of the first and second epitaxial layers, respectively.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-27 | 1993-03-29 | 1993-09-28 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-27 | 1997-03-29 | 1997-09-28 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-27 | 2001-03-29 | 2001-09-28 | $7700.00 | Window Closed / Lapsed |