Patent US4868631A successfully refreshed from Google Patents.
US4868631A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bipolar transistor with shallow junctions and capable of high packing density
Assignee: Texas Instruments Inc
•
Filing: 1989-02-13
•
Granted: 1989-09-19
•
Expires: 2009-02-13
Abstract
Abstract A method of making a bipolar transistor in an LSI or VLSI process which includes forming a buried DUF collector of a first conductivity type, growing an epitaxial layer of a first conductivity type over said DUF collector and forming isolation means around a transistor region. The transistor region includes a trench which at least partially encloses the transistor region and extends through the DUF collector. Emitter and base regions of the first and second conductivity types, respectively, are formed in the epitaxial layer. A collector contact region of the first conductivity is formed in the epitaxial layer and extends down to the buried DUF collector.
Inventors
- 👤 Deems R. Hollingsworth
- 👤 Steve Thompson
- 👤 Harry F. Pang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 21:45
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/051; H10D10/40; H10D10/421; H10D62/00; H10D62/10; H10D62/13; H10D62/137; H10D84/00; H10D84/101; H10D84/121; H10W; H10W10/00; H10W10/01; H10W10/041; H10W10/40
Claims Analysis
Total Claims: 29
Claim 1
Independent Claim
234 words
A bipolar transistor cell formed on a semiconductor substrate of a second conductivity type, comprising: a buried DUF collector region of a first conductivity type in said substrate, an epitaxial layer of a first conductivity type overlying said DUF collector region; isolation means enclosing a transistor region including a trench at least partially enclosing said transistor region and extending through said epitaxial layer and said DUF collector region; said transistor region including emitter and base regions doped with impurities of the first and second conductivity types, respectively, in said epitaxial layer; a collector contact region of the first conductivity type in said transistor region extending through the epitaxial layer to said buried DUF collector region; a layer of silicon oxide overlying said epitaxial layer and a separate surface passivation layer overlying said silicon oxide layer; polysilicon contacts to said emitter and collector contact regions extending through said silicon oxide and passivation layers and having expanded area contact portions extending over respective limited areas of said surface passivation layers, said polysilicon contacts doped with the same impurity as said emitter region; a separate further, thicker layer of silicon oxide overlying said surface passivation layer and having a substantially planarized surface; and metal conductors extending over said planarized surface and through part only of the thickness of the thicker layer of silicon oxide to make contact with said expanded area contact portions of said polysilicon contacts.
Claim 2
Dependent Claim
234 words
A bipolar transistor cell formed on a semiconductor substrate of a second conductivity type, comprising: a buried DUF collector region of a first conductivity type in said substrate, an epitaxial layer of a first conductivity type overlying said DUF collector region; isolation means enclosing a transistor region including a trench at least partially enclosing said transistor region and extending through said epitaxial layer and said DUF collector region; said transistor region including emitter and base regions doped with impurities of the first and second conductivity types, respectively, in said epitaxial layer; a collector contact region of the first conductivity type in said transistor region extending through the epitaxial layer to said buried DUF collector region; a layer of silicon oxide overlying said epitaxial layer and a separate surface passivation layer overlying said silicon oxide layer; polysilicon contacts to said emitter and collector contact regions extending through said silicon oxide and passivation layers and having expanded area contact portions extending over respective limited areas of said surface passivation layers, said polysilicon contacts doped with the same impurity as said emitter region; a separate further, thicker layer of silicon oxide overlying said surface passivation layer and having a substantially planarized surface; and metal conductors extending over said planarized surface and through part only of the thickness of the thicker layer of silicon oxide to make contact with said expanded area contact portions of said polysilicon contacts.
Claim 3
Dependent Claim
16 words
A transistor cell according to claim 1, wherein said buried DUF is an antimony doped region.
Claim 4
Dependent Claim
54 words
A transistor cell according to claim 1, wherein said DUF collector region is in the range of 3 to 31/2 microns thick, is antimony doped to provide a sheet resistance in the range of 15 to 25 ohms per square, and said epitaxial layer is in the range of 1.0 to 1.4 microns thick.
Claim 5
Dependent Claim
57 words
A transistor cell according to claim 1, wherein said base region includes an intrinsic base region having a thickness in the range of approximately 3,000 to 4,000 Angstroms and a sheet resistance of less than approximately 1,000 ohms per square, and an extrinsic base region having a thickness in the range of approximately 4,000 to 5,000 Angstroms.
Claim 6
Dependent Claim
15 words
A transistor cell according to claim 4, wherein said intrinsic base region is boron doped.
Claim 7
Dependent Claim
23 words
A transistor cell according to claim 1, where in said first conductivity type is N-type and said second conductivity type impurity is P-type.
Claim 8
Dependent Claim
14 words
A transistor cell according to claim 1, wherein said trench encloses said transistor region.
Claim 9
Dependent Claim
21 words
A transistor cell according to claim 7, wherein said sidewalls and a bottom of said trench have a thin oxide coating.
Claim 10
Dependent Claim
23 words
A transistor cell according to claim 7, wherein the width of said trench is in the range of 1.5 to 2.0 microns wide.
Claim 11
Dependent Claim
14 words
A transistor cell according to claim 7, wherein said trench is filled with polysilicon.
Claim 12
Dependent Claim
14 words
A transistor cell according to claim 8, wherein said trench is filled with polysilicon.
Claim 13
Dependent Claim
27 words
A transistor cell according to claim 1, wherein said trench, viewed in plan, has corners which are bevelled so as to provide a substantially uniform trench width.
Claim 14
Dependent Claim
37 words
A transistor formed at a face of a semiconductor body and at least partly enclosed by an isolating trench which, viewed in plane, has corners that are bevelled so that the trench has a substantially constant width.
Claim 15
Dependent Claim
37 words
A transistor formed at a face of a semiconductor body and at least partly enclosed by an isolating trench which, viewed in plane, has corners that are bevelled so that the trench has a substantially constant width.
Claim 16
Dependent Claim
17 words
A transistor according to claim 13, wherein the trench is a bevelled corner rectangle, viewed in plan.
Claim 17
Dependent Claim
13 words
A transistor according to claim 13, wherein the trench contains a polysilicon filler.
Claim 18
Dependent Claim
17 words
A transistor according to claim 15, wherein the trench has a thin insulating layer coating its sidewalls.
Claim 19
Dependent Claim
13 words
A transistor according to claim 16, wherein the insulating coating comprises silicon oxide.
Claim 20
Dependent Claim
33 words
A transistor according to claim 13, wherein said face of the semiconductor body is provided by an epitaxial layer on semiconductor substrate, and the trench extends beyond the epitaxial layer into the substrate.
Claim 21
Dependent Claim
53 words
A transistor according to claim 14, wherein said face of the semiconductor body is provided by an epitaxial layer overlying a subsurface collector region in said semiconductor body, said epitaxial layer accommodating either and base regions of said transistor, and wherein said trench extends through said epitaxial layer and said subsurface collector region.
Claim 22
Dependent Claim
233 words
A bipolar transistor cell formed at a face of a semiconductor body, comprising: an n type impurity doped epitaxial layer defining said face of the semiconductor body and overlying a buried, antimony doped, n+ type collector region in said semiconductor body; a p type impurity doped intrinsic base region in said epitaxial layer over said buried collector region; an n+ type impurity doped emitter region in said intrinsic base region; an n+ type impurity doped, collector contact region extending through said epitaxial layer to said buried collector region; an isolation region comprising polysilicon extending into said semiconductor body through the epitaxial layer and said buried collector region, and at least partly surrounding said transistor cell; a layer of silicon oxide overlying said epitaxial layer and a silicon nitride surface passivation layer overlying said silicon oxide layer; polysilicon contacts to said emitter and collector contact regions extending through said silicon oxide and passivation layers and having expanded area contact portions extending over respective limited areas of said surface passivation layer, said polysilicon contacts doped with the same impurity as said emitter region; a further layer of silicon oxide overlying said surface; passivation layer and having a substantially planarized surface; and metal conductors extending over said planarized surface and through part only of the thickness of the further layer of silicon oxide to make contact with said expanded area contact portions of said polysilicon contacts.
Claim 23
Dependent Claim
233 words
A bipolar transistor cell formed at a face of a semiconductor body, comprising: an n type impurity doped epitaxial layer defining said face of the semiconductor body and overlying a buried, antimony doped, n+ type collector region in said semiconductor body; a p type impurity doped intrinsic base region in said epitaxial layer over said buried collector region; an n+ type impurity doped emitter region in said intrinsic base region; an n+ type impurity doped, collector contact region extending through said epitaxial layer to said buried collector region; an isolation region comprising polysilicon extending into said semiconductor body through the epitaxial layer and said buried collector region, and at least partly surrounding said transistor cell; a layer of silicon oxide overlying said epitaxial layer and a silicon nitride surface passivation layer overlying said silicon oxide layer; polysilicon contacts to said emitter and collector contact regions extending through said silicon oxide and passivation layers and having expanded area contact portions extending over respective limited areas of said surface passivation layer, said polysilicon contacts doped with the same impurity as said emitter region; a further layer of silicon oxide overlying said surface; passivation layer and having a substantially planarized surface; and metal conductors extending over said planarized surface and through part only of the thickness of the further layer of silicon oxide to make contact with said expanded area contact portions of said polysilicon contacts.
Claim 24
Dependent Claim
30 words
A transistor cell according to claim 20, wherein said buried collector region is about 3.0 to 3.5 microns thick and said epitaxial layer is about 1 to 1.4 microns thick.
Claim 25
Dependent Claim
33 words
A transistor cell according to claim 20, including a p+ type extrinsic base region contiguous with said intrinsic base region and extending more deeply into said epitaxial layer than said intrinsic base region.
Claim 26
Dependent Claim
21 words
A transistor cell according to claim 20, wherein said isolation region comprises a polysilicon region surrounded by a silicon oxide coating.
Claim 27
Dependent Claim
21 words
A transistor cell according to claim 23, including a channel stop region between said polysilicon region and the underlying semiconductor body.
Claim 28
Dependent Claim
70 words
A transistor cell according to claim 20, wherein said isolation region comprises a polysilicon region surrounded by a silicon oxide coating; said buried collector region is about 3.0 to 3.5 microns thick and said epitaxial layer is about 1.0 to 1.4 microns thick; and including a p+ type extrinsic base region contiguous with the intrinsic base region and extending more deeply into the epitaxial layer than the intrinsic base region.
Claim 29
Dependent Claim
35 words
A transistor cell according to claim 25, wherein the extrinsic base region has a thickness of about 4,000 to 4,500 Angstroms and the intrinsic base region has a thickness of about 3,000 to 4,000 Angstroms.
References Cited (Backward Citations)
US3962779A
Cited
US3980507A
Cited
US3982266A
Cited
US4470062A
Cited
US4595944A
Cited
US4680614A
Cited
US4619036A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-09-18 | 1993-03-20 | 1993-09-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-09-18 | 1997-03-20 | 1997-09-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-09-18 | 2001-03-20 | 2001-09-19 | $7700.00 | Window Closed / Lapsed |