Patent US4862020A successfully refreshed from Google Patents.
US4862020A
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Electronic delay control circuit having pulse width maintenance
Assignee: Tektronix Inc
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Filing: 1988-06-20
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Granted: 1989-08-29
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Expires: 2008-06-20
Abstract
Abstract An electronic delay control circuit provides small, constantly variable delays to an input pulse signal without altering the pulse width of the input signal. The input pulse signal together with a first reference signal are input to three comparators in parallel. The output of one comparator is a pulse signal corresponding to the input pulse signal, and the outputs of the other two comparators are tied together and input to a pulse shaping network to produce delay current pulses for the leading and trailing edges of the input pulse signal. The delay current pulses are added to the output pulse signal to produce a delayed output pulse signal. The delay current pulses are a function of the amount of a constant current steered between the two comparators as determined by a delay control signal.
Inventors
- 👤 Clarence E. Cowan
- 👤 Ronald K. Christensen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 20:55
CPC Classifications
H; H03; H03K; H03K5/00; H03K5/13; H03K5/133; H03K2005/00013; H03K2005/00019; H03K2005/00026; H03K2005/00052; H03K2005/0015; H03K2005/00163; H03K2005/00176; H03K2005/00182; H03K2005/00228
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
68 words
An electronic delay control circuit comprising: means for generating an output current pulse from an input pulse signal; means for generating a delay current pulse from the input pulse signal at each edge of the input pulse signal; and means for adding the output current pulse and the delay current pulse to produce an output pulse signal corresponding to the input pulse signal delayed by a predetermined amount.
Claim 2
Dependent Claim
68 words
An electronic delay control circuit comprising: means for generating an output current pulse from an input pulse signal; means for generating a delay current pulse from the input pulse signal at each edge of the input pulse signal; and means for adding the output current pulse and the delay current pulse to produce an output pulse signal corresponding to the input pulse signal delayed by a predetermined amount.
Claim 3
Dependent Claim
114 words
An electronic delay control circuit as recited in claim 1 wherein the delay current pulse generating means comprises: a first comparator to which the input pulse signal and a first reference signal are input; a second comparator to which the input pulse signal and the first reference signal are input oppositely than to the first comparator; means for steering in response to a delay control signal a control current between the first and second comparators to vary the amplitudes of the outputs from the first and second comparators; and means for shaping the outputs from the first and second comparators to generate the delay current pulse at each edge of the input pulse signal.
Claim 4
Dependent Claim
99 words
An electronic delay control circuit as recited in claim 2 wherein the steering means comprises: a control circuit having complementary outputs to which the delay control signal and a second reference signal are input, one output being coupled to bias the first comparator and the other output being coupled to bias the second comparator; and a constant current source to provide the control current to the control circuit, the amount of the control current being steered to the first and second comparators being a function of the relative levels of the delay control signal and the second reference signal.
Claim 5
Dependent Claim
38 words
An electronic delay control circuit as recited in claim 1 further comprising means for adjusting the pulse width of the input pulse signal independently from the delay of the input pulse signal represented by the output pulse signal.
References Cited (Backward Citations)
US3952213A
Cited
US3906247A
Cited
US4645958A
Cited
US4567378A
Cited
US4675546A
Cited
US4691120A
Cited
US4801827A
Cited
US4797586A
Cited
JPH102017A
Cited
JPH117914A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-28 | 1993-02-27 | 1993-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-28 | 1997-02-27 | 1997-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-28 | 2001-02-27 | 2001-08-29 | $7700.00 | Window Closed / Lapsed |