Patent US4859878A successfully refreshed from Google Patents.
US4859878A
Expired / Lapsed
US
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Bi-MOS levelshift circuit capable of controlling power consumption
Assignee: NEC Electronics Corp
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Filing: 1987-12-17
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Granted: 1989-08-22
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Expires: 2007-12-17
Abstract
Abstract Disclosed is a levelshift circuit comprising a P-channel MOS transistor wherein the source is connected to a high power potential in a low-voltage power circuit, a first N-channel double-diffused field effect transistor wherein the source is connected to a ground potential and the gate and drain are shorted with each other and connected to the drain of the P-channel MOS transistor, a second N-channel double-diffused field effect transistor wherein the structure is the same as that of the first N-channel double-diffused field effect transistor or different only in its gate width at a predetermined ratio from that of the first N-channel double-diffused field effect transistor, the source is connected to the ground potential and the gate is connected to the gate and drain of the second N-channel double-diffused field effect transistor, a PNP transistor wherein the emitter is connected to the high power potential in the high-voltage power circuit, the base is connected to the drain of the second N-channel double-diffused transistor and the collector is connected to a load, and a switch whereby the gate and drain of the first N-channel double-diffused field effect transistor is short-circuited or opened with respect to the ground potential.
Inventors
- 👤 Yoichi Murayama
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-04 13:46
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/567
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
169 words
A Bi-MOS circuit comprising: a MOS field effect transistor having a source connected to a first power potential in a low-voltage power source, a drain and a gate connected to an input terminal; a first double-diffused field effect transistor having a source connected to a reference potential and a gate and a drain connected in common with said drain of said MOS field effect transistor; a second double-diffused field effect transistor having a source connected to said reference potential, a drain and a gate connected to said gate and said drain of said first double-diffused field effect transistor; a bipolar transistor having an emitter connected to a second power potential in a high-voltage power source, a base connected to said drain of said second double-diffused field effect transistor and a collector connected to an output terminal; and a means for controlling a potential level, operatively connected to a junction of said gate of said first double-diffused field effect transistor and said gate of said second double-diffused field effect transistor.
Claim 2
Dependent Claim
169 words
A Bi-MOS circuit comprising: a MOS field effect transistor having a source connected to a first power potential in a low-voltage power source, a drain and a gate connected to an input terminal; a first double-diffused field effect transistor having a source connected to a reference potential and a gate and a drain connected in common with said drain of said MOS field effect transistor; a second double-diffused field effect transistor having a source connected to said reference potential, a drain and a gate connected to said gate and said drain of said first double-diffused field effect transistor; a bipolar transistor having an emitter connected to a second power potential in a high-voltage power source, a base connected to said drain of said second double-diffused field effect transistor and a collector connected to an output terminal; and a means for controlling a potential level, operatively connected to a junction of said gate of said first double-diffused field effect transistor and said gate of said second double-diffused field effect transistor.
Claim 3
Dependent Claim
43 words
The Bi-MOS circuit as claimed in claim 1, wherein structures of said first and second double-diffused field effect transistors are the same except that their channel widths are designed to have a predetermined ratio for controlling a base current of said bipolar transistor.
Claim 4
Dependent Claim
73 words
The Bi-MOS circuit as claimed in claim 2, wherein said MOS transistor is a P-channel MOS transistor, said first power potential is a positive potential of said low-voltage power source, both said first and second double-diffused field effect transistors are of a N-channel type, said reference potential is a ground potential, said bipolar transistor is a PNP bipolar transistor and said second power potential is a positive potential of said high-voltage power source.
Claim 5
Dependent Claim
17 words
The Bi-MOS circuit as claimed in claim 3, wherein said controlling means includes an N-channel MOS transistor.
Claim 6
Dependent Claim
31 words
The Bi-MOS circuit as claimed in claim 3, wherein said controlling means includes a transfer gate having an N-channel MOS transistor and a P-channel MOS transistor which are connected in parallel.
Claim 7
Dependent Claim
17 words
The Bi-MOS circuit as claimed in claim 3, wherein said bipolar transistor is a lateral PNP transistor.
Claim 8
Dependent Claim
107 words
A semiconductor device comprising: an inverter receiving an input signal and supplied with a low-voltage power; a first double-diffused field effect transistor having a source connected to a reference potential and a gate and a drain connected in common to an output of said inverter; a second double-diffused field effect transistor, having a source connected to said reference potential and a gate connected to said drain of said first double-diffused field effect transistor; and a bipolar transistor having an emitter connected to a high-voltage power source, a base connected to a drain of said second double-diffused field effect transistor and a collector connected to an output terminal.
Claim 9
Dependent Claim
107 words
A semiconductor device comprising: an inverter receiving an input signal and supplied with a low-voltage power; a first double-diffused field effect transistor having a source connected to a reference potential and a gate and a drain connected in common to an output of said inverter; a second double-diffused field effect transistor, having a source connected to said reference potential and a gate connected to said drain of said first double-diffused field effect transistor; and a bipolar transistor having an emitter connected to a high-voltage power source, a base connected to a drain of said second double-diffused field effect transistor and a collector connected to an output terminal.
Claim 10
Dependent Claim
53 words
The semiconductor device as claimed in claim 7, wherein channel widths of said first and second double-diffused field effect transistors are designed to control a base current of said bipolar transistor to have a predetermined value and wherein lengths of channels of said first and second double-diffused field effect transistors are the same.
Claim 11
Dependent Claim
31 words
The semiconductor device as claimed in claim 8, wherein both said first and second double-diffused field effect transistors are of an N-channel type, and said bipolar transistor is a PNP transistor.
Claim 12
Dependent Claim
17 words
The semiconductor device as claimed in claim 9, wherein said inverter is of a complementary MOS type.
Claim 13
Dependent Claim
17 words
The semiconductor device as claimed in claim 9, wherein said PNP transistor is a lateral PNP transistor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |