Conductivity-enhanced combined lateral MOS/bipolar transistor

Claim 1

A combined lateral MOS/bipolar transistor, which comprises: a semiconductor substrate of a first conductivity type; a first, floating semiconductor layer of a second conductivity type opposite to that of the first on a first major surface of said substrate; a second semiconductor layer of said first conductivity type on said first layer, the doping level of said second semiconductor layer being at most equal to that of said substrate; a third semiconductor surface layer of said second conductivity type on said second layer; a surface-adjoining channel region of said first conductivity type in said third layer and connected to said second semiconductor layer, said channel region being separated from said first, floating semiconductor layer by said second semiconductor layer; a surface-adjoining source region of said second conductivity type in said channel region; a surface-adjoining drain contact region of said second conductivity type in said third layer and spaced apart from said channel region; an extended drain region formed from a portion of said third layer between said drain contact region and said channel region; an insulating layer on the surface of said transistor and covering at least a first portion of the surface-adjoining channel region located between said source and said extended drain regions; a gate electrode on said insulating layer, over said first portion of the channel region and electrically isolated from said third layer; a base electrode connected to a second portion of said channel region remote from said first region; and source and drain electrodes connected respectively to the source and drain contact regions of the transistor.