US4859617A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Thin-film transistor fabrication process
Assignee: Oki Electric Industry Co Ltd
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Filing: 1988-06-03
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Granted: 1989-08-22
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Expires: 2008-06-03
Abstract
Abstract In a thin-film transistor fabrication process using an amorphous silicon semiconductor layer, after the gate insulation layer is formed and before the a-Si semiconductor layer is formed, the surface of the gate insulation layer is treated with an H 2 plasma. This treatment improves the transistor characteristics.
Inventors
- 👤 Tsutomu Nomoto
- 👤 Mamoru Yosida
- 👤 Mikio Mouri
- 👤 Tsukasa Watanabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 05:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D64/00; H10D64/01; H10D64/013; H10P; H10P95/00; H10P95/94; Y; Y10; Y10S; Y10S438/00; Y10S438/909; Y10S438/91; Y10S438/913
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
133 words
A thin-film transistor fabrication process comprising: a first step for forming a gate electrode on a dielectric substrate; a second step for forming a gate insulation layer over said gate electrode and said substrate; a third step for treating the surface of said gate insulation layer with a 2 plasma consisting of H 2 gas created by glow discharge with an RF power density of from 0.005 w/cm 2 to 0.5 w/cm 2 and for the duration of from 1 minute to 60 minutes; a fourth step for forming an amorphous silicon semiconductor layer over said gate insulating layer; a fifth step for patterning said gate insulation layer and said amorphous silicon semiconductor layer to remove the parts outside the transistor element area; and a sixth step for forming source and drain electrodes.
Claim 2
Dependent Claim
133 words
A thin-film transistor fabrication process comprising: a first step for forming a gate electrode on a dielectric substrate; a second step for forming a gate insulation layer over said gate electrode and said substrate; a third step for treating the surface of said gate insulation layer with a 2 plasma consisting of H 2 gas created by glow discharge with an RF power density of from 0.005 w/cm 2 to 0.5 w/cm 2 and for the duration of from 1 minute to 60 minutes; a fourth step for forming an amorphous silicon semiconductor layer over said gate insulating layer; a fifth step for patterning said gate insulation layer and said amorphous silicon semiconductor layer to remove the parts outside the transistor element area; and a sixth step for forming source and drain electrodes.
Claim 3
Dependent Claim
35 words
A thin-film transistor fabrication process according to claim 1, wherein the third step and the fourth step are performed in the same vacuum apparatus without breaking the vacuum between the third and the fourth steps.
Claim 4
Dependent Claim
24 words
A thin-film transistor fabrication process according to claim 2, wherein the substrate temperature during said third step is from 200° C. to 300° C.
Claim 5
Dependent Claim
24 words
A thin-film transistor fabrication process according to claim 2, wherein the gas flow during said glow discharge is from 10 SSCM to 1000 SSCM.
Claim 6
Dependent Claim
25 words
A thin-film transistor fabrication process according to claim 2, wherein the gas pressure employed in said glow discharge is from 50 pa to 400 pa.
Claim 7
Dependent Claim
38 words
A thin-film transistor fabrication process according to claim 2, wherein the second step is also performed in the same vacuum apparatus as the third and fourth steps without breaking the vacuum between the second and the third steps.
Claim 8
Dependent Claim
24 words
A thin-film transistor fabrication process according to claim 6, wherein the substrate temperature during said third step is from 200° C. to 300° C.
Claim 9
Dependent Claim
24 words
A thin-film transistor fabrication process according to claim 6, wherein the gas flow during said glow discharge is from 10 SSCM to 1000 SSCM.
Claim 10
Dependent Claim
25 words
A thin-film transistor fabrication process according to claim 6, wherein the gas pressure employed in said glow discharge is from 50 pa to 400 pa.
Claim 11
Dependent Claim
34 words
A thin-film transistor fabrication process according to claim 1, further comprising a seventh step for covering, with a protective layer, the entire device that has been formed by the first to the sixth steps.
References Cited (Backward Citations)
US4151058A
Cited
US4113514A
Cited
JPS56155526A
Cited
JPS56156760A
Cited
JPS5712524A
Cited
JPS58137218A
Cited
JPS5927575A
Cited
GB2140202A
Cited
EP0129265A1
Cited
US4605447A
Cited
JPS6016462A
Cited
JPS61133662A
Cited
JPS6251264A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-21 | 1993-02-20 | 1993-08-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-21 | 1997-02-20 | 1997-08-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-21 | 2001-02-20 | 2001-08-22 | $7700.00 | Window Closed / Lapsed |