Patent US4857775A successfully refreshed from Google Patents.
US4857775A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logic integrated circuit device selecting as outputs any two of two inputs and two logical combinations of the inputs
Assignee: Ricoh Co Ltd
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Filing: 1988-04-14
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Granted: 1989-08-15
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Expires: 2008-04-14
Abstract
Abstract A logic integrated circuit device includes a pair of input terminals, an OR gate having a pair of inputs coupled to the pair of input terminals, an exclusive OR gate having a pair of inputs coupled to the pair of input terminals, a first output terminal connected from one of the pair of input terminals through a first gate switch and also from the output of the OR gate through a second gate switch, and a second output terminal connected from the other of the pair of input terminals through a third gate switch and also from the output of the exclusive OR gate through a fourth gate switch. Also provided is a data read out circuit which is operatively coupled to the four gate switches through a switch control circuit. Depending on the condition of the data read out circuit, either one of one of the pair of input signals and a logical sum signal between the pair of input signals is output at the first output terminal and either one of the other of the pair of input signals and an exclusive logical sum signal between the pair of input signals is output at the second output terminal.
Inventors
- 👤 Takeo Obata
- 👤 Akira Takata
- 👤 Takuro Fujioka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:29
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1735; H03K19/1736
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
256 words
A logic integrated circuit device comprising: a first input terminal for receiving a first input logic signal and a second input terminal for receiving a second input logic signal first means receiving said first and second input logic signals and producing a logical sum signal of said first and second input logic signals, and having a first output supplying said logical sum signal; second means receiving said first and second input logic signals and producing an exclusive logical sum signal of said first and second input logic signals, and having a second output supplying said exclusive logical sum signal; first selecting means coupled to said first input terminal and said first output for selecting one of said first input logic signal and said logical sum signal as a first output of said device; and second selecting means coupled to said second input terminal and to said second output for selecting one of said second input logic signal and said exclusive logical sum signal as a second output of said device; wherein said first selecting means includes a first MOS transistor having a first gate connected to a third input terminal and having first source/drain terminals connected between a first pair of predetermined voltages, with a first load connected between one of said first predetermined voltages and one of said first source/drain terminals, and a first inverter having an input connected to the junction between the first load and the first MOS transistor and having an output coupled to said first input terminal and said first output.
Claim 2
Dependent Claim
256 words
A logic integrated circuit device comprising: a first input terminal for receiving a first input logic signal and a second input terminal for receiving a second input logic signal first means receiving said first and second input logic signals and producing a logical sum signal of said first and second input logic signals, and having a first output supplying said logical sum signal; second means receiving said first and second input logic signals and producing an exclusive logical sum signal of said first and second input logic signals, and having a second output supplying said exclusive logical sum signal; first selecting means coupled to said first input terminal and said first output for selecting one of said first input logic signal and said logical sum signal as a first output of said device; and second selecting means coupled to said second input terminal and to said second output for selecting one of said second input logic signal and said exclusive logical sum signal as a second output of said device; wherein said first selecting means includes a first MOS transistor having a first gate connected to a third input terminal and having first source/drain terminals connected between a first pair of predetermined voltages, with a first load connected between one of said first predetermined voltages and one of said first source/drain terminals, and a first inverter having an input connected to the junction between the first load and the first MOS transistor and having an output coupled to said first input terminal and said first output.
Claim 3
Dependent Claim
66 words
The device of claim 1 wherein said first means includes an OR circuit having a first input terminal connected to said first input terminal for receiving said first input logic signal, a second input terminal connected to said second input terminal for receiving said second input logic signal and an output terminal connected to a first output terminal of said device through a first gate switch.
Claim 4
Dependent Claim
67 words
The device of claim 1 wherein said second means includes an exclusive OR circuit having a first input terminal connected to said first input terminal for receiving said first input logic signal, a second input terminal connected to said second input terminal for receiving said second input logic signal and an output terminal connected to a second output terminal of said device through a second gate switch.
Claim 5
Dependent Claim
32 words
The device of claim 2 wherein said first input terminal for receiving said first input logic signal is connected to said first output terminal of said device through a third gate switch.
Claim 6
Dependent Claim
32 words
The device of claim 3 wherein said second input terminal for receiving said second input logic signal is connected to said second output terminal of said device through a fourth gate switch.
Claim 7
Dependent Claim
90 words
The device of claim 1 wherein said second selecting means includes a second MOS transistor having a second gate connected to a fourth input terminal and having second source/drain terminals connected between a second pair of predetermined voltages, with a second load connected between one of said second predetermined voltages and one of said second source/drain terminals, and a second inverter having an input connected to the junction between the second load and the second MOS transistor and an output coupled to said first input terminal and said first output.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-08-14 | 1993-02-13 | 1993-08-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-08-14 | 1997-02-13 | 1997-08-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-08-14 | 2001-02-13 | 2001-08-15 | $7700.00 | Window Closed / Lapsed |