Transistor varactor for dynamics semiconductor storage means

Claim 1

A transistor varactor arrangement for dynamic semiconductor memories on a doped silicon substrate (SU), comprising: at least one field effect transistor having a source (S) region and drain (D) region lying in said doped silicon substrate and having a gate electrode (G) covered on all sides with insulating layers (01,02), said source (S) region being directly contactable from the outside by a terminal (K), and at least one varactor overlapping the gate electrode (G) of the field effect transistor, said at least one varactor being formed as a stacked capacitor and composed of two doped polysilicon layers (P1, P2) with a separating dielectric layer (D2), whereby the upper polysilicon layer (P2) is contactable from the outside and overlaps the lower polysilicon layer (P1) and the sidewalls of the lower polysilicon layer (P1) and overlaps the majority part of the gate electrode (G), an oxide layer (03) produced by oxidation of the sidewalls of the upper polysilicon layer (P2) is provided for insulation of the sidewalls of the upper polysilicon layer (P2) from the terminal (K) to said source region (S), an insulation layer (BPSG) formed on the upper polysilicon layer (P2) except for the contact region (K) and on the oxide layer (03) located on the sidewalls of the upper polysilicon layer (P2), the lower polysilicon layer (P1) partially overlaps the gate electrode (G) and is connected to the drain (D) region of the field effect transistor, and a layer (TS1) containing nitride and/or tetraethylorthosilicate covering said gate electrode (G) which is covered on all sides by said insulating layers (01, 02)