Patent US4853886A successfully refreshed from Google Patents.
US4853886A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital signal processing circuit
Assignee: Toshiba Corp
•
Filing: 1987-02-18
•
Granted: 1989-08-01
•
Expires: 2007-02-18
Abstract
Abstract A multiplier multiplies first binary data X and second binary data Y in 2' complement format, X=(X4, X3, X2, X1) and Y=(Y4, Y3, Y2, Y1) to obtain the product Q=(Q4, Q3, Q2, Q1). An adder/subtractor performs addition/subtraction of third binary data Q'=(Q4, Q3, Q4, Q4) and fourth binary data Z=(Z4, Z3, Z2, Z1) in 2's complement format in response to a control signal. The third binary data includes upper bits and lower bits. The upper bits includes the upper two bits Q4 and Q3 of the multiplication result Q=(Q4, Q3, Q2, Q1). The lower two bits include the inverted most significant bit Q4 of the multiplication result. When the adder/subtractor operates in the adder mode, the inverted most significant bit Q4 of the multiplication result is applied as a carry input to the adder/subtractor. In the subtractor mode, the most significant bit Q4 of the multiplication result is applied as a carry bit to the adder/subtractor.
Inventors
- 👤 Hiroshi Shigehara
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 20:25
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/544; G06F7/499; G06F7/49942; G06F7/49947
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
200 words
A circuit for multiplying first and second binary data in 2's complement format to obtain a multiplication result, generating a third data in 2's complement format from that result, and adding or subtracting the third data to or from a fourth data in 2's complement format, comprising: a multiplier for multiplying said first and second binary data in 2's complement format and deleting a predetermined number of least significant bits of the actual multiplication result to obtain a virtual multiplication result; an adder/subtractor for performing addition/subtraction of said third binary data and said fourth binary data in 2's complement format in response to a control signal, the most significant bits of said third binary data being said virtual multiplication result and a plurality of lower bits of said third binary data being an inverted most significant bit of said virtual multiplication result; and means for supplying to said adder/subtractor said inverted most significant bit of said virtual multiplication result as the least significant bit when said adder/subtractor operates in an adder mode, and for supplying to said adder/subtractor said most significant bit of said virtual multiplication result as the least significant bit when said adder/subtractor operates in a subtractor mode.
Claim 2
Dependent Claim
200 words
A circuit for multiplying first and second binary data in 2's complement format to obtain a multiplication result, generating a third data in 2's complement format from that result, and adding or subtracting the third data to or from a fourth data in 2's complement format, comprising: a multiplier for multiplying said first and second binary data in 2's complement format and deleting a predetermined number of least significant bits of the actual multiplication result to obtain a virtual multiplication result; an adder/subtractor for performing addition/subtraction of said third binary data and said fourth binary data in 2's complement format in response to a control signal, the most significant bits of said third binary data being said virtual multiplication result and a plurality of lower bits of said third binary data being an inverted most significant bit of said virtual multiplication result; and means for supplying to said adder/subtractor said inverted most significant bit of said virtual multiplication result as the least significant bit when said adder/subtractor operates in an adder mode, and for supplying to said adder/subtractor said most significant bit of said virtual multiplication result as the least significant bit when said adder/subtractor operates in a subtractor mode.
Claim 3
Dependent Claim
24 words
A digital signal processing circuit according to claim 1, wherein said least significant bit supplied to said adder/subtractor is supplied as a carry input.
Claim 4
Dependent Claim
203 words
A circuit for multiplying first and second binary data in 2's complement format to obtain a multiplication result, processing the multiplication result to provide a third data in 2's complement format, and adding or subtracting the third data to or from a fourth data in 2's complement format, comprising: a multiplier for multiplying said first and second binary data in 2's complement format and providing a multiplication result; an adder/subtractor for performing addition/subtraction of said third binary data and said fourth binary data in 2's complement format in response to a control signal, a plurality of most significant bits of said third binary data being a predetermined number of most significant bits of said multiplication result and a plurality of lower significant bits of said third binary data being a logical product of a logical sum of a plurality of least significant bits of said multiplication result with an inverted most significant bit of said multiplication result; and means for supplying to said adder/subtractor said logical product as the least significant bit when said adder/subtractor operates in an adder mode, and for supplying to said adder/subtractor an inverted logical product as the least significant bit when said adder/subtractor operates in a subtractor mode.
Claim 5
Dependent Claim
203 words
A circuit for multiplying first and second binary data in 2's complement format to obtain a multiplication result, processing the multiplication result to provide a third data in 2's complement format, and adding or subtracting the third data to or from a fourth data in 2's complement format, comprising: a multiplier for multiplying said first and second binary data in 2's complement format and providing a multiplication result; an adder/subtractor for performing addition/subtraction of said third binary data and said fourth binary data in 2's complement format in response to a control signal, a plurality of most significant bits of said third binary data being a predetermined number of most significant bits of said multiplication result and a plurality of lower significant bits of said third binary data being a logical product of a logical sum of a plurality of least significant bits of said multiplication result with an inverted most significant bit of said multiplication result; and means for supplying to said adder/subtractor said logical product as the least significant bit when said adder/subtractor operates in an adder mode, and for supplying to said adder/subtractor an inverted logical product as the least significant bit when said adder/subtractor operates in a subtractor mode.
Claim 6
Dependent Claim
23 words
A digital signal processing circuit according to claim 3, wherein said least significant bit is supplied to said adder/subtractor as a carry input.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-31 | 1993-01-30 | 1993-08-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-31 | 1997-01-30 | 1997-08-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-31 | 2001-01-30 | 2001-08-01 | $7700.00 | Window Closed / Lapsed |