Apparatus for symmetrically truncating two's complement binary signals as for use with interleaved quadrature signals

Claim 2

Apparatus for truncating an M-bit two's complement binary signal to (M-N) bits wherein the MSB of the M bit signal is a sign bit and M and N are integers, said apparatus comprising: an input port for applying said M-bit binary signal; means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state; means coupled to said input port, and responsive to said control signal, for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

Claim 3

The apparatus set forth in claim 1 wherein the means for producing said control signal is a logical AND gate having a first input terminal connected to the MSB of said M-bit binary signal and a second input coupled to said N LSB's of said M-bit binary signal.

Claim 4

The apparatus set forth in claim 2 wherein the second input of said logical AND gate is coupled to said N LSB's of said M-bit binary signal by a logical OR gate having respective input terminals connected to said N LSB's and an output terminal connected to said AND gate.

Claim 5

The apparatus set forth in claim 3 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary adder having an input port with at least (M-N) binary input connections coupled to respective ones of the (M-N) MSB's of the means for applying said M-bit binary signal and having a carry-in input terminal connected to said AND gate.

Claim 6

The apparatus set forth in claim 2 wherein the integer N equals one and includes a second similar apparatus in cascade connection therewith.

Claim 7

The apparatus set forth in claim 1 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary incrementing circuit having at least M-N input terminals connected to the (M-N) MSB's of said means for applying an M-bit binary signal and having a incrementing-control input terminal connected to the means for producing said control signal.

Claim 8

The apparatus set forth in claim 1 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary adder having an input port with at least (M-N) binary input connections coupled to the (M-N) MSB's of the means for applying said M-bit binary signal and having a carry-in input terminal coupled for receiving said control signal.

Claim 9

In a digital TV receiver including a source of two's complement binary signals and circuitry for processing said binary signals, which circuitry tends to increase the number of bit positions of the processed signal to M bit positions, apparatus for symmetrically truncating said M-bit binary signals to (M-N) bits where M and N are integers, said apparatus comprising: an input port for applying said M-bit binary signals; means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state; means coupled to said input port, and responsive to said control signal for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

Claim 10

In a digital TV receiver including a source of two's complement binary signals and circuitry for processing said binary signals, which circuitry tends to increase the number of bit positions of the processed signal to M bit positions, apparatus for symmetrically truncating said M-bit binary signals to (M-N) bits where M and N are integers, said apparatus comprising: an input port for applying said M-bit binary signals; means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state; means coupled to said input port, and responsive to said control signal for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

Claim 11

The apparatus set forth in claim 8 wherein the means for producing said control signal is a logical AND gate having a first input terminal connected to the MSB of said M-bit binary signal and a second input coupled to said N LSB's of said M-bit binary signal.

Claim 12

The apparatus set forth in claim 9 wherein the second input of said logical AND gate is coupled to said N LSB's of said M-bit binary signal by a logical OR gate having respective input terminals connected to said N LSB's and an output terminal connected to said AND gate.

Claim 13

The apparatus set forth in claim 8 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary incrementing circuit having at least M-N input terminals for applying the (M-N) MSB's of said M-bit binary signal and having a incrementing-control input terminal connected to the means for producing said control signal.

Claim 14

The apparatus set forth in claim 8 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary adder having an input port with at least (M-N) binary input connections coupled to receive the (M-N) MSB's of said M-bit binary signal and having a carry-in input terminal coupled for receiving said control signal.

Claim 15

In a digital TV receiver including a source of two's complement binary signal corresponding to composite video signal and digital circuitry for processing a chrominance component of said composite binary signals, which circuitry tends to increase the number of bit positions of the processed binary signal to M bit positions, apparatus for symmetrically truncating said M-bit binary signals to (M-N) bits, where M an N are integers, said apparatus comprising: an input port for applying said M-bit binary signals; means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state; means coupled to said input port, and responsive to said control signal for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

Claim 16

In a digital TV receiver including a source of two's complement binary signal corresponding to composite video signal and digital circuitry for processing a chrominance component of said composite binary signals, which circuitry tends to increase the number of bit positions of the processed binary signal to M bit positions, apparatus for symmetrically truncating said M-bit binary signals to (M-N) bits, where M an N are integers, said apparatus comprising: an input port for applying said M-bit binary signals; means coupled to said input port, and responsive to the N LSB's of said M-bit binary signal and the MSB of said M-bit binary signal for producing a control signal whenever at least one of said N LSB's of the M-bit binary signal and the MSB of said M-bit binary signal are concurrently in a logical one state; means coupled to said input port, and responsive to said control signal for incrementing by one unit the (M-N) MSB's of said M-bit binary signal and providing the incremented (M-N) MSB's as a truncated (M-N)-bit binary signal, and in the absence of said control signal providing the (M-N) MSB's of said M-bit binary signal as a truncated (M-N)-bit binary signal.

Claim 17

The apparatus set forth in claim 13 wherein the means for producing said control signal is a logical AND gate having a first input terminal connected to the MSB of said M-bit binary signal and a second input coupled to said N LSB's of said M-bit binary signal.

Claim 18

The apparatus set forth in claim 14 wherein the second input of said logical AND gate is coupled to said N LSB's of said M-bit binary signal by a logical OR gate having respective input terminals connected to said N LSB's and an output terminal connected to said AND gate.

Claim 19

The apparatus set forth in claim 13 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary incrementing circuit having at least M-N input terminals for applying the (M-N) MSB's of said M-bit binary signal and having a incrementing-control input terminal connected to the means for producing said control signal.

Claim 20

The apparatus set forth in claim 13 wherein the means for incrementing the (M-N) MSB's of said M-bit binary signal is a binary adder having an input port with at least (M-N) binary input connections coupled to receive the (M-N) MSB's of said M-bit binary signal and having a carry-in input terminal coupled for receiving said control signal.