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US4280190A
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Incrementer/decrementer circuit
Assignee: Motorola Solutions Inc
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Filing: 1979-08-09
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Granted: 1981-07-21
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Expires: 1999-08-09
Abstract
Abstract An increment/decrement circuit is provided which is implemented using CMOS transistors. The circuit has a minimum of interconnect lines to an adjoining increment/decrement circuit and also uses a reduced number of transistors. The increment/decrement circuit has a carry/borrow generator and has an increment/decrement output portion. The carry/borrow generator uses only three transistors plus an inverter and two coupling transistors. The increment/decrement output portion uses only six transistors.
Inventors
- 👤 Philip S. Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:11
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/505; G06F7/5055; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/321
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
381 words
An incrementer/decrementer circuit, comprising: a first input for receiving a carry-in signal; a second input for receiving an increment input; a third input for receiving a decrement input; a fourth and a fifth input for receiving complementary inputs; a first and a second output for providing outputs for the incrementer/decrementer circuit; a third output for providing a carry-out output; a first and a second transistor coupled in series between the fourth and fifth inputs, the first transistor having a gate electrode coupled to the third input, the second transistor having a gate electrode coupled to the second input, the first and second transistors forming a first node therebetween; a third and fourth transistor coupled in series between the first node and a first power supply terminal, the third and fourth transistors forming a second node therebetween and having gate electrodes coupled to the first input; an inverter coupled between the second node and the third output; feedback means coupled to the inverter to form a latch with the inverter; a fifth and sixth transistor having a first and a second current carrying electrode and a gate electrode, the first electrode of the fifth and sixth transistor being coupled to the second output, the gate electrode of the fifth transistor being coupled to the fourth input, the gate electrode of the sixth transistor being coupled to the first input, the second electrode of the fifth transistor being coupled to the first input, the second electrode of the sixth transistor being coupled to the fourth input; seventh and eighth transistors having first electrodes coupled to the first output, and having second and gate electrodes, the gate electrode of the seventh transistor being coupled to the first input, the seventh transistor having its second electrode coupled to the fifth input, the gate electrode of the eighth transistor being coupled to the fifth input, the second electrode of the eighth transistor being coupled to the first input; and ninth and tenth transistors having first electrodes coupled to the first voltage terminal, the ninth transistor having a second electrode coupled to the second output and having a gate electrode coupled to the first output, the tenth transistor having a second electrode coupled to the first output and having a gate electrode coupled to the second output.
Claim 2
Dependent Claim
381 words
An incrementer/decrementer circuit, comprising: a first input for receiving a carry-in signal; a second input for receiving an increment input; a third input for receiving a decrement input; a fourth and a fifth input for receiving complementary inputs; a first and a second output for providing outputs for the incrementer/decrementer circuit; a third output for providing a carry-out output; a first and a second transistor coupled in series between the fourth and fifth inputs, the first transistor having a gate electrode coupled to the third input, the second transistor having a gate electrode coupled to the second input, the first and second transistors forming a first node therebetween; a third and fourth transistor coupled in series between the first node and a first power supply terminal, the third and fourth transistors forming a second node therebetween and having gate electrodes coupled to the first input; an inverter coupled between the second node and the third output; feedback means coupled to the inverter to form a latch with the inverter; a fifth and sixth transistor having a first and a second current carrying electrode and a gate electrode, the first electrode of the fifth and sixth transistor being coupled to the second output, the gate electrode of the fifth transistor being coupled to the fourth input, the gate electrode of the sixth transistor being coupled to the first input, the second electrode of the fifth transistor being coupled to the first input, the second electrode of the sixth transistor being coupled to the fourth input; seventh and eighth transistors having first electrodes coupled to the first output, and having second and gate electrodes, the gate electrode of the seventh transistor being coupled to the first input, the seventh transistor having its second electrode coupled to the fifth input, the gate electrode of the eighth transistor being coupled to the fifth input, the second electrode of the eighth transistor being coupled to the first input; and ninth and tenth transistors having first electrodes coupled to the first voltage terminal, the ninth transistor having a second electrode coupled to the second output and having a gate electrode coupled to the first output, the tenth transistor having a second electrode coupled to the first output and having a gate electrode coupled to the second output.
Claim 3
Dependent Claim
17 words
The incrementer/decrementer circuit of claim 1 wherein the increment and decrement inputs are complements of each other.
Claim 4
Dependent Claim
14 words
The incrementer/decrementer circuit of claim 1 wherein all the transistors are field effect transistors.
Claim 5
Dependent Claim
32 words
The incrementer/decrementer circuit of claim 1 wherein the first, second, fourth, fifth, sixth, seventh and eighth transistors are N channel transistors, and the third, ninth, and tenth transistors are P channel transistors.
Claim 6
Dependent Claim
44 words
The incrementer/decrementer circuit of claim 1 wherein the feedback means is a P channel transistor having a first electrode coupled to the first power supply terminal, a second electrode coupled to the second node, and having a gate electrode coupled to the third output.
Claim 7
Dependent Claim
289 words
An incrementer/decrementer circuit having a carry input, a carry output, a first and a second control input, a first and second data input and a first and a second data output, comprising: a first node; first controllable means for coupling the first data input to the first node; second controllable means for coupling the second data input to the first node; means for providing a carry-out to the carry output and having a first and a second input, the first input being coupled to the first node and the second input being coupled to the carry input; a first and a second field effect transistor coupled in series between a power supply terminal and the first data input, the first and second transistors forming a second node therebetween which is coupled to the second output, the first transistor having a gate electrode coupled to the carry input; a third field effect transistor coupled between the second node and the carry input and having a gate electrode coupled to the first data input; a fourth and fifth field effect transistor coupled between the power supply terminal and the second data input and forming a third node therebetween, the third node being coupled to the first output, the fourth transistor having a gate electrode coupled to the carry input, the fifth transistor having a gate electrode coupled to the second node, the second transistor having a gate electrode coupled to the third node; and a sixth transistor coupled between the third node and the carry input and having a gate electrode coupled to the second data input, wherein the first controllable means is controlled by the first control input and the second controllable means is controlled by the second control input.
Claim 8
Dependent Claim
289 words
An incrementer/decrementer circuit having a carry input, a carry output, a first and a second control input, a first and second data input and a first and a second data output, comprising: a first node; first controllable means for coupling the first data input to the first node; second controllable means for coupling the second data input to the first node; means for providing a carry-out to the carry output and having a first and a second input, the first input being coupled to the first node and the second input being coupled to the carry input; a first and a second field effect transistor coupled in series between a power supply terminal and the first data input, the first and second transistors forming a second node therebetween which is coupled to the second output, the first transistor having a gate electrode coupled to the carry input; a third field effect transistor coupled between the second node and the carry input and having a gate electrode coupled to the first data input; a fourth and fifth field effect transistor coupled between the power supply terminal and the second data input and forming a third node therebetween, the third node being coupled to the first output, the fourth transistor having a gate electrode coupled to the carry input, the fifth transistor having a gate electrode coupled to the second node, the second transistor having a gate electrode coupled to the third node; and a sixth transistor coupled between the third node and the carry input and having a gate electrode coupled to the second data input, wherein the first controllable means is controlled by the first control input and the second controllable means is controlled by the second control input.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-07-20 | 1985-01-19 | 1985-07-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-07-20 | 1989-01-19 | 1989-07-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-07-20 | 1993-01-19 | 1993-07-21 | $7700.00 | Window Closed / Lapsed |