US4153939A
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Incrementer circuit
Assignee: NEC Corp
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Filing: 1978-02-09
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Granted: 1979-05-08
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Expires: 1998-02-09
Abstract
Abstract An incrementer circuit receives m digit binary input signals and derives m digit binary output signals. First to (m-1)th carry signals are generated, and the h-th (where h is integer between 2 and m-1) carry signal generator includes a transfer gate which transfers one of th (h-1)th carry signal and a reference signal in response to the h-th digit input signal as the h-th carry signal. The incrementer circuit is characterized by low power consumption and low propagation delay.
Inventors
- 👤 Eiichi Kudou
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 22:27
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/32; G06F9/321; G06F7/00; G06F7/38; G06F7/48; G06F7/50
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
302 words
An incrementer circuit comprising first to m-th (where m is an integer of 2 or more) input terminals for receiving first to m-th digit binary input signals respectively, first to m-th output terminals for deriving first to m-th digit binary output signals respectively, first means for generating a first carry signal, second to (m-1)th means for generating second to (m-1)th carry signal respectively, the h-th (where h denotes each of the integers from 2 to m-1) carry signal generating means including a first insulated-gate field effect transistor, the gate and one of the source and drain of said first field effect transistor being supplied with said h-th digit input signal and with the (h-1)th carry signal respectively, a second insulated-gate field effect transistor, the gate and one of the source and drain of said second field effect transistor being supplied with the inverted signal of said h-th digit input signal and with a reference voltage corresponding to a "0" binary signal respectively, a carry signal output terminal connected to the other of the source and drain of said first transistor and the other of the source and drain of said second transistor in common, a first transfer gate circuit for transferring the inverted signal of said first digit input signals to said first output terminal, and second to m-th gating means, the k-th (where k denotes each of the integers from 2 to m-1) gating means including a third insulated-gate field effect transistor for transferring the k-th digit input signal to said k-th output terminal in response to a "0" binary signal of the (k-1)th carry signal and a fourth insulated-gate field effect transistor for transferring the inverted signal of said k-th digit input signal to said k-th output terminal in response to a "1" binary signal of the (k-1)th carry signal.
Claim 2
Dependent Claim
302 words
An incrementer circuit comprising first to m-th (where m is an integer of 2 or more) input terminals for receiving first to m-th digit binary input signals respectively, first to m-th output terminals for deriving first to m-th digit binary output signals respectively, first means for generating a first carry signal, second to (m-1)th means for generating second to (m-1)th carry signal respectively, the h-th (where h denotes each of the integers from 2 to m-1) carry signal generating means including a first insulated-gate field effect transistor, the gate and one of the source and drain of said first field effect transistor being supplied with said h-th digit input signal and with the (h-1)th carry signal respectively, a second insulated-gate field effect transistor, the gate and one of the source and drain of said second field effect transistor being supplied with the inverted signal of said h-th digit input signal and with a reference voltage corresponding to a "0" binary signal respectively, a carry signal output terminal connected to the other of the source and drain of said first transistor and the other of the source and drain of said second transistor in common, a first transfer gate circuit for transferring the inverted signal of said first digit input signals to said first output terminal, and second to m-th gating means, the k-th (where k denotes each of the integers from 2 to m-1) gating means including a third insulated-gate field effect transistor for transferring the k-th digit input signal to said k-th output terminal in response to a "0" binary signal of the (k-1)th carry signal and a fourth insulated-gate field effect transistor for transferring the inverted signal of said k-th digit input signal to said k-th output terminal in response to a "1" binary signal of the (k-1)th carry signal.
Claim 3
Dependent Claim
40 words
The incrementor circuit according to claim 1, wherein said first means includes a wiring means connected between said first input terminal and the one of the source and drain of said first transistor in said second carry signal generating means.
Claim 4
Dependent Claim
282 words
An incrementer circuit comprising first to m-th (where m is an integer of 2 or more than 2) input terminals for receiving first to m-th digit binary input signals respectively, first to m-th output terminals, first means for generating a first carry signal, second to (m-1)th means for generating second to (m-1)th carry signal, respectively, the h-th (where h denotes each of the integers from 2 to m-1) carry signal generating means including a first insulated-gate field effect transistor, the gate and one of the source and drain of said first field effect transistor being supplied with said h-th digit input signal and with the (h-1)th carry signal respectively, a second insulated-gate field effect transistor, the gate and one of the source and drain of said second transistor being supplied with the inverted signal of said h-th digit input signal and with a reference voltage corresponding to a "1" binary signal respectively, and a carry signal output terminal connected to the other of the source and drain of said first transistor and the other of the source and drain of said second transistor in common, first transfer means for transferring said first digit input signal to said first output terminal, and second to m-th gating means, the k-th (where k denotes each of the integers from 2 to m-1) gating means including a third insulated-gate field effect transistor for transferring the k-th digit input signal to said k-th output terminal in response to a "1" binary signal of the (k-1)th carry signal, and a fourth insulated-gate field effect transistor for transferring the inverted signal of said k-th digit input signal in response to a "0" binary signal of the (k-1)the carry signal.
Claim 5
Dependent Claim
282 words
An incrementer circuit comprising first to m-th (where m is an integer of 2 or more than 2) input terminals for receiving first to m-th digit binary input signals respectively, first to m-th output terminals, first means for generating a first carry signal, second to (m-1)th means for generating second to (m-1)th carry signal, respectively, the h-th (where h denotes each of the integers from 2 to m-1) carry signal generating means including a first insulated-gate field effect transistor, the gate and one of the source and drain of said first field effect transistor being supplied with said h-th digit input signal and with the (h-1)th carry signal respectively, a second insulated-gate field effect transistor, the gate and one of the source and drain of said second transistor being supplied with the inverted signal of said h-th digit input signal and with a reference voltage corresponding to a "1" binary signal respectively, and a carry signal output terminal connected to the other of the source and drain of said first transistor and the other of the source and drain of said second transistor in common, first transfer means for transferring said first digit input signal to said first output terminal, and second to m-th gating means, the k-th (where k denotes each of the integers from 2 to m-1) gating means including a third insulated-gate field effect transistor for transferring the k-th digit input signal to said k-th output terminal in response to a "1" binary signal of the (k-1)th carry signal, and a fourth insulated-gate field effect transistor for transferring the inverted signal of said k-th digit input signal in response to a "0" binary signal of the (k-1)the carry signal.
Claim 6
Dependent Claim
26 words
The incrementer circuit according to claim 3, wherein said first transfer means includes wiring means connected between said first input terminal and said first output terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-05-07 | 1982-11-06 | 1983-05-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-05-07 | 1986-11-06 | 1987-05-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-05-07 | 1990-11-06 | 1991-05-08 | $7700.00 | Window Closed / Lapsed |