US4598382A
Expired / Lapsed
US
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Multiplying circuit
Assignee: Toshiba Corp
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Filing: 1983-08-10
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Granted: 1986-07-01
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Expires: 2003-08-10
Abstract
Abstract A multiplying circuit comprises an array circuit for producing a product of a multiplicand and multiplier by adding respective partial products together each of a multiplicand in each bit and a multiplier in each bit. The array circuit produces only an (n+1) or more bits of the product, where n denotes a positive integer which is not greater than the bit number of the multiplicand and the bit number of the multiplier. The multiplying circuit comprises a circuit for producing a binary compensation signal representing an integral value closest to a real number given by {(n-1)+(1/2.sup.n)}/2 and a circuit for adding the compensation signal to the output from the array circuit.
Inventors
- 👤 Tai Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 18:54
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/52; G06F7/523; G06F7/53; G06F7/5306; G06F7/499; G06F7/49942
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
105 words
A multiplying circuit comprising: array circuit means for producing a binary signal corresponding to at least (n+1)-th bits of a product of a multiplicand and multiplier by adding partial products together each having a multiplicand bit and a multiplier bit, where n is any positive integer which is not greater than the smaller one of the bit number of the multiplicand and the bit number of the multiplier; means for producing a binary compensation signal representing an integral value corresponding to a real number given by (n-1)+(1/2.sup.n)/2; and means for adding the binary signal produced from said array circuit means and the binary compensation signal.
Claim 2
Dependent Claim
105 words
A multiplying circuit comprising: array circuit means for producing a binary signal corresponding to at least (n+1)-th bits of a product of a multiplicand and multiplier by adding partial products together each having a multiplicand bit and a multiplier bit, where n is any positive integer which is not greater than the smaller one of the bit number of the multiplicand and the bit number of the multiplier; means for producing a binary compensation signal representing an integral value corresponding to a real number given by (n-1)+(1/2.sup.n)/2; and means for adding the binary signal produced from said array circuit means and the binary compensation signal.
Claim 3
Dependent Claim
60 words
A multiplying circuit according to claim 1, in which said array circuit means comprises a plurality of unit circuits each comprised of an AND gate for producing a partial product of a multiplicand in each bit and a multiplier in each bit, and a full adder for adding an output of the AND gate and output of a preceding stage.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-06-30 | 1989-12-30 | 1990-07-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-06-30 | 1993-12-30 | 1994-07-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-06-30 | 1997-12-30 | 1998-07-01 | $7700.00 | Window Closed / Lapsed |