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US4849800A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor component

Assignee: BBC Brown Boveri AG Switzerland
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Filing: 1987-09-18
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Granted: 1989-07-18
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Expires: 2007-09-18
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Abstract

Abstract In a semiconductor component, which has various differently doped layers (2, 3, 4, 5) within a semiconductor substrate, an improvement of the electrical properties is achieved, wherein the thickness of the substrate in the current-carrying region is locally reduced by a deep etch well (10), the original mechanical stability of the semiconductor substrate largely remaining retained.

Inventors

  • 👤 C. Christiaan Abbas
  • 👤 Jens Gobrecht
  • 👤 Jan Voboril
  • 👤 Horst Gruning

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 12:53
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/141; H10D62/142; H10D62/117; H10W; H10W90/00; H10W90/701; H10W90/731; H10W90/736

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 213 words
A power semiconductor device comprising: a large-area semiconductor substrate of a first thickness; a plurality of differently doped layers provided within said substrate between an anode and a cathode with a thyristor layer sequence including an anode layer, a p-base layer, an n-base layer and a cathode layer, said layer sequence defining a thyristor which can be switched off via a gate; said cathode layer and p-base layer comprising a step-like gate-cathode structure, in which a plurality of cathode fingers project out of and are separated by a recessed gate plane thus forming a control structure, said control structure subdivided into a plurality of separated control zones, each of said control zones comprising a plurality of said cathode fingers; said first thickness of said semiconductor substrate being reduced by a plurality of deep etch wells introduced into said semiconductor substrate on the side of said anode opposite respective of said control zones, each etch well having an area approximately equal to the area of the control zone opposite thereto; said etch wells reducing said thickness over an area of said semiconductor substrate which comprises a plurality of said cathode fingers; said semiconductor substrate being soldered onto a metal substrate with said anode side; and said etch wells being completely filled in with solder.
Claim 2
Dependent Claim 213 words
A power semiconductor device comprising: a large-area semiconductor substrate of a first thickness; a plurality of differently doped layers provided within said substrate between an anode and a cathode with a thyristor layer sequence including an anode layer, a p-base layer, an n-base layer and a cathode layer, said layer sequence defining a thyristor which can be switched off via a gate; said cathode layer and p-base layer comprising a step-like gate-cathode structure, in which a plurality of cathode fingers project out of and are separated by a recessed gate plane thus forming a control structure, said control structure subdivided into a plurality of separated control zones, each of said control zones comprising a plurality of said cathode fingers; said first thickness of said semiconductor substrate being reduced by a plurality of deep etch wells introduced into said semiconductor substrate on the side of said anode opposite respective of said control zones, each etch well having an area approximately equal to the area of the control zone opposite thereto; said etch wells reducing said thickness over an area of said semiconductor substrate which comprises a plurality of said cathode fingers; said semiconductor substrate being soldered onto a metal substrate with said anode side; and said etch wells being completely filled in with solder.
Claim 3
Dependent Claim 39 words
A power semiconductor device according to claim 1, comprising: said anode layer being p-doped and said n-base layer being weakly n-doped; and said thickness reduction of said semiconductor substrate being correlated to a thickness reduction of said n-base layer.
Claim 4
Dependent Claim 23 words
A power semiconductor device according to claim 2, comprising a strongly n-doped stopping layer provided between said anode layer and said n-base layer.
Claim 5
Dependent Claim 29 words
A power semiconductor device according to claim 2, wherein said thickness reduction of said n-base layer leads to a thickness of said n-base layer of less than 200 μm.

References Cited (Backward Citations)

CA632366A Cited
DE1208409B Cited
US3553536A Cited
US3769563A Cited
EP0029932A1 Cited
JPS5676568A Cited
EP0064231A2 Cited
EP0066721A2 Cited
EP0082419A2 Cited
EP0121068A1 Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-17 1993-01-16 1993-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-17 1997-01-16 1997-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-17 2001-01-16 2001-07-18 $7700.00 Window Closed / Lapsed

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