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US4849658A
Expired / Lapsed
US
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Dynamic logic circuit including bipolar transistors and field-effect transistors
Assignee: Hitachi Ltd
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Filing: 1987-08-04
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Granted: 1989-07-18
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Expires: 2007-08-04
Abstract
Abstract A dynamic logic circuit is provided which is arranged to realize high speed operation. At least one bipolar transistor is provided having a collector, a base and an emitter, with the collector-emitter current path connected between the output of the dynamic logic circuit and a first potential. A precharging device is coupled between a second potential and the output of the dynamic logic circuit to precharge the output according to at least one clock signal which periodically changes its state. Further, at least two field-effect transistors are provided, wherein one assumes an on or off state opposite to that of the precharging means in response to the clock signal while the other operates in response to at least one input signal. The two field-effect transistors have their source-drain current paths connected between the output of the dynamic logic circuit and the base of the bipolar transistor.
Inventors
- 👤 Masahiro Iwamura
- 👤 Takashi Hotta
- 👤 Hideo Maejima
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 15:22
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F7/5016; G11; G11C; G11C7/00; G11C7/12; H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/094; H03K19/096; H03K19/0963; H03K19/173; H03K19/177; H03K19/17704; H03K19/17708; H03K19/17716; H03K19/1772; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
150 words
A dynamic logic circuit containing at least one bipolar transistor and a plurality of field-effect transistors, comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level according to at least one clock signal which periodically changes its state; and at least two field-effect transistors having their source-drain current paths connected in series between the output of said dynamic logic circuit and the base of said bipolar transistor, one of said field-effect transistors assuming an on or off state opposite to that of said precharging means in response to the clock signal, and the other of said field-effect transistors operating in response to at least one input signal.
Claim 2
Dependent Claim
150 words
A dynamic logic circuit containing at least one bipolar transistor and a plurality of field-effect transistors, comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level according to at least one clock signal which periodically changes its state; and at least two field-effect transistors having their source-drain current paths connected in series between the output of said dynamic logic circuit and the base of said bipolar transistor, one of said field-effect transistors assuming an on or off state opposite to that of said precharging means in response to the clock signal, and the other of said field-effect transistors operating in response to at least one input signal.
Claim 3
Dependent Claim
50 words
A dynamic logic circuit according to claim 1, further comprising a discharging means connected between the base of said bipolar transistor and a third potential to form a current path for discharging the stored charge of said bipolar transistor when said bipolar transistor changes its state from on to off.
Claim 4
Dependent Claim
157 words
A dynamic logic circuit containing at least one bipolar transistor and a plurality of field-effect transistors, comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; a precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level according to at least one clock signal which periodically changes its state; and at least one first field-effect transistor which assumes an on or off state opposite to that of said precharging means in response to the clock signal; and at least one second field-effect transistor which operates in response to at least one input signal; whereby the source-drain current paths of said first and second field-effect transistors are connected in series between the output of said dynamic logic circuit and the base of said bipolar transistor.
Claim 5
Dependent Claim
157 words
A dynamic logic circuit containing at least one bipolar transistor and a plurality of field-effect transistors, comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; a precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level according to at least one clock signal which periodically changes its state; and at least one first field-effect transistor which assumes an on or off state opposite to that of said precharging means in response to the clock signal; and at least one second field-effect transistor which operates in response to at least one input signal; whereby the source-drain current paths of said first and second field-effect transistors are connected in series between the output of said dynamic logic circuit and the base of said bipolar transistor.
Claim 6
Dependent Claim
53 words
A dynamic logic circuit according to claim 3, further comprising a leak current compensation means coupled between the second potential and the output of said dynamic logic circuit, and including means to prevent output variations of said dynamic logic circuit when at least one of said first and second field-effect transistors is off.
Claim 7
Dependent Claim
50 words
A dynamic logic circuit according to claim 3, further comprising a discharging means connected between the base of said bipolar transistor and a third potential to form a current path for discharging the stored charge of said bipolar transistor when said bipolar transistor changes its state from on to off.
Claim 8
Dependent Claim
45 words
A dynamic logic circuit according to claim 3, wherein said bipolar transistor has a collector and an emitter of a first conductivity type and a base of a second conductivity type, and wherein said first and second field-effect transistors are of the first conductivity type.
Claim 9
Dependent Claim
22 words
A dynamic logic circuit according to claim 3, wherein said precharging means is made up of at least one third field-effect transistor.
Claim 10
Dependent Claim
27 words
A dynamic logic circuit according to claim 6, wherein said precharging means is made up of at least one third field-effect transistor of the second conductivity type.
Claim 11
Dependent Claim
158 words
A data processing apparatus integrated in at least one semiconductor substrate and containing a dynamic logic circuit; the dynamic logic circuit comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; a precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level in response to at least one clock signal which periodically changes its state; and at least two field-effect transistors having their source-drain current path connected between the output of said dynamic logic circuit and the base of said bipolar transistor, one of said field-effect transistors being coupled to assume an on or off state opposite to that of said precharging means in response to the clock signal, and the other of said field-effect transistors operating in response to at least one input signal.
Claim 12
Dependent Claim
158 words
A data processing apparatus integrated in at least one semiconductor substrate and containing a dynamic logic circuit; the dynamic logic circuit comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; a precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level in response to at least one clock signal which periodically changes its state; and at least two field-effect transistors having their source-drain current path connected between the output of said dynamic logic circuit and the base of said bipolar transistor, one of said field-effect transistors being coupled to assume an on or off state opposite to that of said precharging means in response to the clock signal, and the other of said field-effect transistors operating in response to at least one input signal.
Claim 13
Dependent Claim
162 words
A data processing apparatus integrated in at least one semiconductor substrate and containing a dynamic logic circuit; said dynamic logic circuit comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; a precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level in response to at least one clock signal which periodically changes its state; at least one first field-effect transistor which assumes an on or off state opposite to that of said precharging means in response to the clock signal; and at least one second field-effect transistor which operates in response to at least one input signal; whereby the source-drain current paths of said first and second field-effect transistors are connected in series between the output of said dynamic logic circuit and the base of said bipolar transistor.
Claim 14
Dependent Claim
162 words
A data processing apparatus integrated in at least one semiconductor substrate and containing a dynamic logic circuit; said dynamic logic circuit comprising: a bipolar transistor having a collector, a base and an emitter with the collector-emitter current path connected between an output of said dynamic logic circuit and a first potential; a precharging means coupled between a second potential and the output of said dynamic logic circuit for precharging said output to a predetermined level in response to at least one clock signal which periodically changes its state; at least one first field-effect transistor which assumes an on or off state opposite to that of said precharging means in response to the clock signal; and at least one second field-effect transistor which operates in response to at least one input signal; whereby the source-drain current paths of said first and second field-effect transistors are connected in series between the output of said dynamic logic circuit and the base of said bipolar transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-17 | 1993-01-16 | 1993-07-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-17 | 1997-01-16 | 1997-07-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-17 | 2001-01-16 | 2001-07-18 | $7700.00 | Window Closed / Lapsed |