EP0064870A2
Expired / Lapsed
EP
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Digital semiconductor integrated circuit device
Assignee: Nippon Gakki Co Ltd
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Filing: 1982-05-07
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Granted: —
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Expires: 2002-05-07
Abstract
Abstract A digital semiconductor integrated circuit device comprising a common semiconductor substrate, a dynamic MOS circuit block (10) comprising a MOS-FET, and a static bipolar circuit block (12) comprising a bipolar transistor or an SIT which is operated in a "bipolar mode" and cascade-connected to said dynamic MOS circuit block (10) in said common semiconductor substrate. The device is such that, by setting the timing of clock pulses, the logical operations of these circuit blocks are performed in a timed relationship with each other. Thus, this integrated circuit device can be produced with minimized dependency of its operation velocity upon the design of these circuit blocks and can perform a high-speed operation and can provide a high packing density.
Inventors
- 👤 Terumoto Nonaka
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 19:09
CPC Classifications
G; G11; G11C; G11C19/00; G11C19/28; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
53 words
A digital semiconductor integrated circuit device, comprising: a common semiconductor substrate; and at least one dynamic MOS circuit block and at least one static bipolar circuit block both formed in said common substrate, said dynamic MOS circuit block and said static bipolar circuit block being operated in a timed relationship with each other.
Claim 2
Dependent Claim
53 words
A digital semiconductor integrated circuit device, comprising: a common semiconductor substrate; and at least one dynamic MOS circuit block and at least one static bipolar circuit block both formed in said common substrate, said dynamic MOS circuit block and said static bipolar circuit block being operated in a timed relationship with each other.
Claim 3
Dependent Claim
25 words
A device according to claim 1, in which said dynamic MOS circuit block and said static bipolar circuit block are coupled together in cascade fashion.
Claim 4
Dependent Claim
16 words
A device according to claim 2, in which said static circuit block comprises a bipolar transistor.
Claim 5
Dependent Claim
24 words
A device according to claim 2, in which said static circuit block comprises a normally-off static induction transmitter which is operated in bipolar mode.
Claim 6
Independent Claim
69 words
A device according to any one of claims 2 to 4, in which said dynamic MOS circuit block transmits a digital signal to said bipolar static circuit block in accordance with a first clock pulse, and said static bipolar circuit block, upon receipt of said digital signal, processes said digital signal in accordance with a second clock pulse having a phase identical with that of said first clock pulse.
Claim 7
Independent Claim
61 words
A device according to any one of claims 2 to 4, in which said bipolar static circuit block transmits a digital signal to said dynamic MOS circuit block in accordance with a first clock pulse, and said dynamic MOS circuit block processes said digital signal in accordance with a second clock pulse having a phase opposite to said first clock pulse.
Claim 8
Independent Claim
61 words
A device according to claim.5 or 6, in which said dynamic MOS circuit block comprises dynamic MOS shift registers whose timing of operation is controlled by two phase clock pulses having inverted phases relative to each other, and said static bipolar circuit block comprises a static bipolar shift register whose timing of operation is controlled by a single phase clock pulse.
Claim 9
Dependent Claim
113 words
A device according to claim 7, in which: the first dynamic MOS shift register, the static bipolar shift register and the second dynamic MOS shift register are cascaded in this order, each said dynamic MOS shift register comprises a cascade connection of signal-transmitting stages each comprises a MOS transistor and a MOS inverter, and arranged so that those adjacently disposed MOS transistors are controlled as to timing of their operations by mutually phase-inverted clock pulses, respectively, and said static bipolar shift register comprises a combination of delay flip-flops formed with a combination of NAND gates employing bipolar transistors whose timing of operation is controlled by a single-phase clock pulse, thereby to be edge-triggered.
Claim 10
Dependent Claim
34 words
A device according to claim 8, in which said bipolar transistor is an ordinary bipolar transistor or a transistor comprised of a normally-off type static induction transistor which is operated in a bipolar mode.
References Cited (Backward Citations)
No citation records indexed.
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