Patent US4845381A successfully refreshed from Google Patents.
US4845381A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Voltage level shifting circuit
Assignee: NXP BV
•
Filing: 1987-10-01
•
Granted: 1989-07-04
•
Expires: 2007-10-01
Abstract
Abstract In the present invention, a voltage level shifting circuit is disclosed. The voltage level shifting circuit comprises a first inventer and a second inverter with each inverter having a P-type MOS transistor and an N-type MOS transistor. Each of the inverters has an input port, an output port, a first voltage port and a second voltage port. The source of the P-type MOS transistor or N-type MOS transistor of each inverter is connected to the first voltage port. The voltage level shifting circuit also comprises two MOS transistors of the same conductivity type as the transistors of the inverter whose source is connected to the first voltage port. Each of the MOS transistors has a source, a drain and a gate with the drain connected to the first voltage port of each of the inverters. The sources of the first and second MOS transistors are connected together and to a high voltage level, such as V pp . Cross-coupling is provided by connecting the gate of the MOS transistor to the output port of the other inverter. The output is taken from the output port of the second inverter.
Inventors
- 👤 Peter Cuevas
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 04:05
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356165
Claims Analysis
Total Claims: 30
Claim 1
Independent Claim
475 words
A voltage level shifting circuit for receiving an input signal, varying between a first voltage, and second voltage and producing an output signal, varying between said first voltage and a third voltage, said circuit comprising: a first inverter means having an input port, an output port, a first voltage port and a second voltage port; said first inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a first MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said first inverter means; a second inverter means having an input port, an output port, a first voltage port and a second voltage port, said second inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type, said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a second MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said second inverter means; said source of said first and second MOS transistor means are connected together and to a voltage source for said third voltage; first coupling means for connecting the gate of said first MOS transistor means to said output port of said second inverter means; second coupling means for connecting the gate of said second MOS transistor means to said output port of said first inverter means; and said input signal is supplied to said input port of said first inverter means; an inverted input signal is supplied to said input port of said second inverter means; said second voltage port of said first and second inverter means are connected together to a voltage source for said first voltage; and said output port of said second inverter means provides said output a signal.
Claim 2
Dependent Claim
475 words
A voltage level shifting circuit for receiving an input signal, varying between a first voltage, and second voltage and producing an output signal, varying between said first voltage and a third voltage, said circuit comprising: a first inverter means having an input port, an output port, a first voltage port and a second voltage port; said first inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a first MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said first inverter means; a second inverter means having an input port, an output port, a first voltage port and a second voltage port, said second inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type, said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a second MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said second inverter means; said source of said first and second MOS transistor means are connected together and to a voltage source for said third voltage; first coupling means for connecting the gate of said first MOS transistor means to said output port of said second inverter means; second coupling means for connecting the gate of said second MOS transistor means to said output port of said first inverter means; and said input signal is supplied to said input port of said first inverter means; an inverted input signal is supplied to said input port of said second inverter means; said second voltage port of said first and second inverter means are connected together to a voltage source for said first voltage; and said output port of said second inverter means provides said output a signal.
Claim 3
Dependent Claim
14 words
The circuit of claim 1 wherein said first conductivity type is P conductivity type.
Claim 4
Dependent Claim
23 words
The circuit of claim 2 wherein said third voltage is greater than said second voltage and wherein said first voltage is ground potential.
Claim 5
Dependent Claim
81 words
The circuit of claim 2 wherein said first inverter means includes an N type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor connected to the drain of said N type MOS transistor and to said output port; and said source of said N type MOS transistor is connected to said second voltage port.
Claim 6
Dependent Claim
82 words
The circuit of claim 2 wherein said second inverter means includes an N type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said N type MOS transistor is connected to said second voltage port.
Claim 7
Dependent Claim
14 words
The circuit of claim 1 wherein said first conductivity type is N conductivity type.
Claim 8
Dependent Claim
25 words
The circuit of claim 6 wherein said third voltage is less than said second voltage and wherein said first voltage is a positive voltage potential.
Claim 9
Dependent Claim
82 words
The circuit of claim 6 wherein said first inverter means includes a P type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said P type MOS transistor is connected to said second voltage port.
Claim 10
Dependent Claim
82 words
The circuit of claim 6 wherein said second inverter means includes a P type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said P type MOS transistor is connected to said second voltage port.
Claim 11
Dependent Claim
486 words
A voltage level shifting circuit for receiving an input signal, varying between a first voltage and a second voltage and producing an output signal, varying between said first voltage and a third voltage, said circuit comprising: a first inverter means having an input port, an output port, a first voltage port and a second voltage port; said first inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a first MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said first inverter means; a second inverter means having an input port, an output port, a first voltage port and a second voltage port, said second inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a second MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said second inverter means; said source of said first and second MOS transistor means are connected together and to a voltage source for said third voltage; first coupling means for connecting the gate of said first MOS transistor means to said output port of said second inverter means; second coupling means for connecting the gate of said second MOS transistor means to said output port of said first inverter means; and said input signal is supplied to said input port of said first inverter means and to said second voltage port of said second inverter means; said input port of said second inverter means is connected to a voltage source for said second voltage; said second voltage port of said first inverter means is connected to a voltage source for said first voltage; and said output port of said second inverter means provides said output signal.
Claim 12
Dependent Claim
486 words
A voltage level shifting circuit for receiving an input signal, varying between a first voltage and a second voltage and producing an output signal, varying between said first voltage and a third voltage, said circuit comprising: a first inverter means having an input port, an output port, a first voltage port and a second voltage port; said first inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a first MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said first inverter means; a second inverter means having an input port, an output port, a first voltage port and a second voltage port, said second inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a second MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said second inverter means; said source of said first and second MOS transistor means are connected together and to a voltage source for said third voltage; first coupling means for connecting the gate of said first MOS transistor means to said output port of said second inverter means; second coupling means for connecting the gate of said second MOS transistor means to said output port of said first inverter means; and said input signal is supplied to said input port of said first inverter means and to said second voltage port of said second inverter means; said input port of said second inverter means is connected to a voltage source for said second voltage; said second voltage port of said first inverter means is connected to a voltage source for said first voltage; and said output port of said second inverter means provides said output signal.
Claim 13
Dependent Claim
14 words
The circuit of claim 10 wherein said first conductivity type is P conductivity type.
Claim 14
Dependent Claim
23 words
The circuit of claim 11 wherein said third voltage is greater than said second voltage and wherein said first voltage is ground potential.
Claim 15
Dependent Claim
81 words
The circuit of claim 11 wherein said first inverter means includes an N type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor connected to the drain of said N type MOS transistor and to said output port; and said source of said N type MOS transistor is connected to said second voltage port.
Claim 16
Dependent Claim
82 words
The circuit of claim 11 wherein said second inverter means includes an N type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said N type MOS transistor is connected to said second voltage port.
Claim 17
Dependent Claim
14 words
The circuit of claim 10 wherein said first conductivity type is N conductivity type.
Claim 18
Dependent Claim
25 words
The circuit of claim 15 wherein said third voltage is less than said second voltage and wherein said first voltage is a positive voltage potential.
Claim 19
Dependent Claim
82 words
The circuit of claim 15 wherein said first inverter means includes a P type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said P type MOS transistor is connected to said second voltage port.
Claim 20
Dependent Claim
82 words
The circuit of claim 15 wherein said second inverter means includes a P type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said P type MOS transistor is connected to said second voltage port.
Claim 21
Dependent Claim
475 words
A voltage level shifting circuit for receiving an input signal, varying between a first voltage and a second voltage and producing an output signal, varying between said first voltage and a third voltage, said circuit comprising: a first inverter means having an input port, an output port, a first voltage port and a second voltage port; said first inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a first MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said first inverter means; a second inverter means having an input port, an output port, a first voltage port and a second voltage port, said second inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a second MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said inverter means; said source of said first and second MOS transistor means are connected together and to a voltage source for said third voltage; first coupling means for connecting the gate of said first MOS transistor means to said output port of said second inverter means; second coupling means for connecting the gate of said second MOS transistor means to said output port of said first inverter means; and said input signal is supplied to said second voltage port of said second inverter means, an inverter input signal is supplied to said second voltage port of said first inverter means; said input ports of said first and second inverter means are connected together and to a voltage source for said second voltage; said output port of said second inverter means provides said output signal.
Claim 22
Dependent Claim
475 words
A voltage level shifting circuit for receiving an input signal, varying between a first voltage and a second voltage and producing an output signal, varying between said first voltage and a third voltage, said circuit comprising: a first inverter means having an input port, an output port, a first voltage port and a second voltage port; said first inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a first MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said first inverter means; a second inverter means having an input port, an output port, a first voltage port and a second voltage port, said second inverter means having a plurality of MOS transistors with at least one transistor of a first conductivity type and at least one transistor of a second conductivity type; said one transistor of the first conductivity type having a source, a drain and a gate with said source connected to said first voltage port; said transistor of the second conductivity type having a source, a drain and a gate with the source connected to the second voltage port, and said gate of said transistor of the first conductivity type connected to said gate of said transistor of the second conductivity type; a second MOS transistor means of the first conductivity type having a source, a drain and a gate with said drain connected to said first voltage port of said inverter means; said source of said first and second MOS transistor means are connected together and to a voltage source for said third voltage; first coupling means for connecting the gate of said first MOS transistor means to said output port of said second inverter means; second coupling means for connecting the gate of said second MOS transistor means to said output port of said first inverter means; and said input signal is supplied to said second voltage port of said second inverter means, an inverter input signal is supplied to said second voltage port of said first inverter means; said input ports of said first and second inverter means are connected together and to a voltage source for said second voltage; said output port of said second inverter means provides said output signal.
Claim 23
Dependent Claim
14 words
The circuit of claim 19 wherein said first conductivity type is P conductivity type.
Claim 24
Dependent Claim
23 words
The circuit of claim 20 wherein said third voltage is greater than said second voltage and wherein said first voltage is ground potential.
Claim 25
Dependent Claim
82 words
The circuit of claim 20 wherein said first inverter means includes an N type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said N type MOS transistor is connected to said second voltage port.
Claim 26
Dependent Claim
82 words
The circuit of claim 20 wherein said second inverter means includes an N type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said N type MOS transistor is connected to said second voltage port.
Claim 27
Dependent Claim
14 words
The circuit of claim 19 wherein said first conductivity type is N conductivity type.
Claim 28
Dependent Claim
25 words
The circuit of claim 24 wherein said third voltage is less than said second voltage and wherein said first voltage is a positive voltage potential.
Claim 29
Dependent Claim
82 words
The circuit of claim 24 wherein said first inverter means includes a P type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistors are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said P type MOS transistor is connected to said second voltage port.
Claim 30
Dependent Claim
82 words
The circuit of claim 24 wherein said second inverter means includes a P type MOS transistor having a gate, a source and a drain; said gate of said N type and P type transistor are connected together and to said input port; said drain of said P type MOS transistor is connected to the drain of said N type MOS transistor and to said output port; and said source of said P type MOS transistor is connected to said second voltage port
References Cited (Backward Citations)
US4476401A
Cited
US4616148A
Cited
US4656374A
Cited
US4695744A
Cited
US4689504A
Cited
US4697108A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-03 | 1993-01-02 | 1993-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-03 | 1997-01-02 | 1997-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-03 | 2001-01-02 | 2001-07-04 | $7700.00 | Window Closed / Lapsed |