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US4843595A
Expired / Lapsed
US
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Data reading circuit for semiconductor memory device
Assignee: Fujitsu Ltd
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Filing: 1987-01-20
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Granted: 1989-06-27
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Expires: 2007-01-20
Abstract
Abstract A data reading circuit for a semiconductor memory device includes: a first input terminal and a second input terminal each receiving complementary signals. A first and a second current mirror type sense amplifiers, each including a reference node, an output terminal, a first transistor connected with the reference node, and a second transitor connected with the output terminal. A gate of the first transitor of the first current mirror type sense amplifier and a gate of the second transistor of the second current mirror type sense amplifier are connected to the first input terminal. A gate of the second transistor of the first current mirror type sense amplifier and a gate of the first transitor of the second current mirror type sense amplifier are connected to a second input terminal. The data reading circuit further includes a short-circuiting transistor connected between the reference nodes of both the first and the second current mirror type sense amplifiers. The first short-circuiting transistor is able to conduct therethrough temporarily by receiving a clock signal at a gate.
Inventors
- 👤 Atsushi Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 21:54
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/06; G11C7/062; G11C7/1048
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
178 words
A data reading circuit for a semiconductor memory device comprising: a first input terminal and a second input terminal each receiving complementary signals; a first and a second current mirror type sense amplifiers, each of said current mirror type sense amplifiers including, a reference node, an output terminal, a first transistor connected with said reference node, and a second transistor connected with said output terminal, a gate of said first transistor of said first current mirror type sense amplifier and a gate of said second transistor of said second current mirror type sense amplifier being connected to said first input terminal, and a gate of said second transistor of said first current mirror type sense amplifier and a gate of said first transistor of said second current mirror type sense amplifier being connected to said second input terminal; and a first short-circuiting transistor connected between the reference nodes of both said first and said second current mirror type sense amplifiers, said first short-circuiting transistor being able to conduct therethrough temporarily by receiving a clock signal at a gate.
Claim 2
Dependent Claim
178 words
A data reading circuit for a semiconductor memory device comprising: a first input terminal and a second input terminal each receiving complementary signals; a first and a second current mirror type sense amplifiers, each of said current mirror type sense amplifiers including, a reference node, an output terminal, a first transistor connected with said reference node, and a second transistor connected with said output terminal, a gate of said first transistor of said first current mirror type sense amplifier and a gate of said second transistor of said second current mirror type sense amplifier being connected to said first input terminal, and a gate of said second transistor of said first current mirror type sense amplifier and a gate of said first transistor of said second current mirror type sense amplifier being connected to said second input terminal; and a first short-circuiting transistor connected between the reference nodes of both said first and said second current mirror type sense amplifiers, said first short-circuiting transistor being able to conduct therethrough temporarily by receiving a clock signal at a gate.
Claim 3
Dependent Claim
62 words
A data reading circuit for a semiconductor memory device according to claim 1, wherein said data reading circuit further comprises a second short-circuiting transistor, said second short-circuiting transistor being connected between the output terminals of said first and said second current mirror type sense amplifiers and said second short-circuiting transistor is conducted therethrough temporarily by receiving said clock signal at said gate.
Claim 4
Dependent Claim
111 words
A data reading circuit for a semiconductor memory device according to claim 1, wherein said first current mirror type sense amplifier is composed of transistors Q3 to Q7, said second current mirror type sense amplifier is composed of transistors Q8 to Q12, a transistor Q13 can carry out a short-circuit operation between the output lines of said first sense amplifier and said second sense amplifier, and transistors Q3, Q4, Q7, Q8, Q9, Q12 and Q13 are N-channel MOS transistors, while transistors Q5, Q6, Q10 and Q11 P-channel MOS transistors and said first and second sense amplifiers are both current mirror type sense amplifiers which are formed by a respective CMOS circuit.
Claim 5
Dependent Claim
39 words
A data reading circuit for a semiconductor memory device according to claim 1, wherein said data reading circuit further comprises a third short-circuiting transistor and said third short-circuiting transistor is connected between said first and said second input terminals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-06-26 | 1992-12-26 | 1993-06-27 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-06-26 | 1996-12-26 | 1997-06-27 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-06-26 | 2000-12-26 | 2001-06-27 | $7700.00 | Window Closed / Lapsed |