A clocked static memory

Claim 2

A clocked static memory comprising: a memory matrix (10)including a plurality of static memory cells (11) arranged in rows and columns; a plurality of word select lines (12) in said memory matrix, each of said word. select lines being connected to all memory cells in a row; a plurality of bit lines (13, 14) arranged in pairs with a column of cells arranged between each pair of bit lines and each memory cell in each of said columns being connected between said associated pair of bit lines,characterised in that, a logic circuit (50) is connected between said pair of bit lines to provide a memory status output signal, thereby providing tracking of data output timing despite parameter variations of memory elements in the clocked static memory.

Claim 3

A clocked static memory according to claim 1, further comprising a pair of data lines connected between the said pair of bit lines, the logic circuit being connected to the said data lines.

Claim 4

A clocked static memory according to claim 2, in whih the pair of data lines is connected to the pair of bit lines through control gates (28,29).

Claim 5

A clocked static memory according to claim 1, 2 or 3, further comprising a plurality of presense amplifiers (22) with a presense amplifier connected between each of the said pair of bit lines in each column, and a sense clock line (27) parallel to said word select lines (12) the sense clock line being connected to the presense amplifiers.

Claim 6

A clocked static memory according to claims 1, 2, 3 or 4 wherein the logic circuit is comprised of a NAND circuit; and further comprising a pair of precharging devices (21) in each pair of bit lines and a voltage source (Vcc) for precharging said bit lines with a logical "1" level.

Claim 7

A clocked static memory according to claim 1, 2, 3 or 4 wherein the logic circuit comprises a logic OR circuit; and further comprising a pair of precharging devices (21) in each pair of bit lines and a voltage source (Vcc) for precharging the bit lines with a logical "0" level.

Claim 8

A clocked static memory according to claim 1, 2, 3 or 4 wherein the logic circuit comprises a NOR circuit and an inverter gate, and further comprising a pair of precharging devices (21) in each pair of bit lines and a voltage source (Vcc) for precharging the bit lines with a logical "0" level.

Claim 9

A clocked static memory according to any one of the preceding claims, in which each memory cell has a first pair of logic steering transistors (19A, 19B), the said word select lines being loaded with the said steering transistors in the memory cells and each of a plurality of presense amplifiers (22) is connected between a pair of bit lines in a column, each of the presense amplifiers comprising a second pair of logic steering transistors (25, 26), and characterised in that the clocked static memory further comprises a single sense clock line (27) parallel to the word select lines (12), the sense clock line being connected to each of said second pairs of transistors (25, 26) of the presense amplifiers (22) in each column, a sense drive circuit (40) connected to said sense clock line (27), said sense drive circuit including a transistor (T5) for providing a delayed clock signal output on said sense clock line, a row drive circuit (31) connected to said plurality of word select lines (12) and a column drive circuit (35) connected to control gates (28, 29) connected.to the plurality of bit lines, the row and column drive circuits being comprised of a transistor with higher driving capability than that of the said transistor in said sense drive circuit.

Claim 10

A clocked static memory according to any one of the preceding claims, comprising a buffer amplifier following the said logic circuit and providing at its output the memory status output signals.