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US4841347A Expired / Lapsed US ⏱️ 0.0 years remaining

MOS VLSI device having shallow junctions and method of making same

Assignee: General Electric Co
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Filing: 1985-10-30
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Granted: 1989-06-20
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Expires: 2005-10-30
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Abstract

Abstract A semiconductor device and method of making is disclosed wherein the semiconductor device includes a MOSFET with very shallow source and drain regions. The high sheet resistivity normally associated with such shallow regions is obviated by growing an epitaxial layer directly from the surface of the shallow source and drain regions, highly doping the layer, then forming a layer of refractory metal silicide on the epitaxial layer. The resulting structure yields a MOSFET having very shallow source and drain regions with very low sheet resistance.

Inventors

  • 👤 Sheng T. Hsu

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 12:20
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D30/00; H10D30/01; H10D30/021; H10D30/027; H10D30/0275; H10D64/00; H10D64/01; H10D64/011; H10D64/0111; H10D64/0112; H10D64/20; H10D64/23; H10D64/251; H10D64/258

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 130 words
An MOS field effect transistor (FET) comprising a body with a surface, an insulated gate on said surface, source and drain regions in said body adjacent said gate extending downwardly from said surface to a predetermined depth and spaced to define a channel region therebetween, two spaced apart layers of doped single cryatalline silicon, one of which is on said surface of said source region in ohmic contact therewith and spaced from said gate and the other of which is on said surface of said drain region in ohmic contact therewith and spaced from said gate, and a layer of refractory metal silicide on said layer of single crystalline silicon, said two layers of doped single crystalline silicon being more highly doped than both of said source and drain regions.
Claim 2
Dependent Claim 130 words
An MOS field effect transistor (FET) comprising a body with a surface, an insulated gate on said surface, source and drain regions in said body adjacent said gate extending downwardly from said surface to a predetermined depth and spaced to define a channel region therebetween, two spaced apart layers of doped single cryatalline silicon, one of which is on said surface of said source region in ohmic contact therewith and spaced from said gate and the other of which is on said surface of said drain region in ohmic contact therewith and spaced from said gate, and a layer of refractory metal silicide on said layer of single crystalline silicon, said two layers of doped single crystalline silicon being more highly doped than both of said source and drain regions.
Claim 3
Dependent Claim 22 words
The device set forth in claim 1 wherein said depth of said source and drain regions is less than about 100 nm.
Claim 4
Dependent Claim 18 words
The device set forth in claim 2 wherein said layer of single crystalline silicon is an epitaxial layer.
Claim 5
Dependent Claim 22 words
The device set forth in claim 3 wherein said epitaxial layer has a thickness of about 150 nm to about 300 nm.
Claim 6
Dependent Claim 22 words
The device set forth in claim 4 wherein said depth of said source and drain regions is less than about 50 nm.
Claim 7
Dependent Claim 18 words
The device set forth in claim 5 wherein said epitaxial layer has a thickness of about 200 nm.
Claim 8
Dependent Claim 23 words
The device set forth in claim 6 wherein a layer of silicon oxide is interposed said gate and said surface of said body.
Claim 9
Dependent Claim 25 words
The device set forth in claim 7 wherein a layer of silicon oxide is interposed said gate and said layer of doped single crystalline silicon.
Claim 10
Dependent Claim 21 words
The device set forth in claim 8 including a layer of silicon nitride disposed on a top surface of said gate.

References Cited (Backward Citations)

US4384301A Cited
US4458410A Cited
US4476475A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-06-19 1992-12-19 1993-06-20 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-06-19 1996-12-19 1997-06-20 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-06-19 2000-12-19 2001-06-20 $7700.00 Window Closed / Lapsed

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