Multiple redundant clock circuit

Claim 2

A data processing device comprising: a. four parallel-operating data processing modules; and b. a multiple redundant clock device comprising: i. four clock circuits, each clock circuit being assigned to a respective one of the parallel-operating data processing modules and comprising: A. means for determining a binary two-thirds majority signal from output clock signals of the three other clock circuits; B. means for generating a clock function signal under control of said majority signal, said generating means gradually adjusting said clock function signal to reduce a deviation, between said majority signal and said clock function signal, by a deviation reduction factor which is substantially smaller than one for each signal transition in the majority signal; C. output means, responsive to the clock function signal, for supplying a respective local output clock signal; and ii. an interconnection network for communicating the output clock signals between the clock circuits.

Claim 3

A multiple redundant clock device for use in a data processing device which includes four parallel-operating data processing modules, the clock device comprising: a. four clock circuits, each clock circuit being assigned to a respective one of the parallel-operating data processing modules and comprising: i. means for determining a binary two-thirds majority signal from output clock signals of the three other clock circuits; ii. means for generating a clock function signal under control of said majority signal, said generating means gradually adjusting said clock function signal to reduce a deviation, between said majority signal and said clock function signal, by a deviation reduction factor which is substantially smaller than one for each signal transition in the majority signal; iii. output means, responsive to the clock function signal, for supplying a respective local output clock signal; and b. an interconnection network for communicating the output clock signals between the clock circuits.

Claim 4

A multiple redundant clock device for use in a data processing device which includes four parallel-operating data processing modules, the clock device comprising: a. four clock circuits, each clock circuit being assigned to a respective one of the parallel-operating data processing modules and comprising: i. means for determining a binary two-thirds majority signal from output clock signals of the three other clock circuits; ii. means for generating a clock function signal under control of said majority signal, said generating means gradually adjusting said clock function signal to reduce a deviation, between said majority signal and said clock function signal, by a deviation reduction factor which is substantially smaller than one for each signal transition in the majority signal; iii. output means, responsive to the clock function signal, for supplying a respective local output clock signal; and b. an interconnection network for communicating the output clock signals between the clock circuits.

Claim 5

The device of claim 1 or 2 wherein the deviation reduction factor is less than or equal to 0.5.

Claim 6

The device of claim 1 or 2 wherein the deviation reduction factor is less than or equal to 0.1 for each signal transition in the majority signal.

Claim 7

The device of claim 1 or 2 wherein: a. the generating means comprises an LRC band filter, having an input coupled to receive the majority decision signal; and b. the output means comprises a buffer at an output of the LCR band filter.

Claim 8

The device of claim 1 or 2 wherein: a. the means for generating includes a crystal having a first connection coupled with an output of the determining means; and b. the output means comprises a second, buffered connection of the crystal.

Claim 9

The device of claim 6 wherein the output means further comprises: a. a capacitor; b. a feedback element; c. a buffer having an input at the second connection of the crystal and an output at which the local output clock signal is supplied; and d. a voltage divider coupled with the second connection of the crystal, the voltage divider having a first side for coupling to a first potential, and a second side for coupling via the capacitor to a second potential and for coupling via the feedback element to the output of the buffer.

Claim 10

The device of claim 1 or 2 wherein: a. said output means is an output line; b. the generating means comprises: i. a buffer element having an output connected to said output line; ii. a crystal unit comprising: A. a first connection directly connected to the output line; B. a second connection connected to said output line via the buffer element; C. a variable capacitor coupled between the first and second connections; iii. a difference determining device having a first input coupled to the output line and and a second input coupled to receive the majority signal and having an output; iv. an integrator element coupled to the output of the difference determining device and to a control input of the variable capacitor, so that the difference determining means controls the variable capacitor via the intergrator element.

Claim 11

The device of claim 1 or 2 wherein: a. the output means comprises a buffer element having an output at which the local clock signal is supplied; and b. the generating means comprises a phase-locked loop which comprises: i. a controlled oscillator, having an output coupled to an input of the buffer element and having an input; ii. a multiplier element, having a first input coupled to the output of the controlled oscillator, a second input coupled to receive the majority signal, and an output; and iii. a low-pass filter having an input coupled with the output of the multiplier element and an output coupled with the input of the controlled oscillator.

Claim 12

A clock circuit for use, with three other analogous clock circuits in a multiple redundant clock device which produces output clock signals for four parallel-operating data processing modules in a data processing device, each clock circuit being assigned to a respective one of the parallel-operating data processing modules, the clock circuit comprising: a. means for determining a binary two-thirds majority signal from the output clock signals of the three other clock circuits; b. means for generating a clock function signal under control of said majority signal, said generating means gradually adjusting said clock function signal to reduce a deviation, between said majority signal and said clock function signal, by a deviation reduction factor which is substantially smaller than one for each signal transition in the majority signal; and c. output means, responsive to the clock function signal, for supplying a respective local output clock signal.

Claim 13

A clock circuit for use, with three other analogous clock circuits in a multiple redundant clock device which produces output clock signals for four parallel-operating data processing modules in a data processing device, each clock circuit being assigned to a respective one of the parallel-operating data processing modules, the clock circuit comprising: a. means for determining a binary two-thirds majority signal from the output clock signals of the three other clock circuits; b. means for generating a clock function signal under control of said majority signal, said generating means gradually adjusting said clock function signal to reduce a deviation, between said majority signal and said clock function signal, by a deviation reduction factor which is substantially smaller than one for each signal transition in the majority signal; and c. output means, responsive to the clock function signal, for supplying a respective local output clock signal.

Claim 14

The clock circuit of claim 10 wherein the deviation reduction factor is less than or equal to 0.5.

Claim 15

The clock circuit of claim 10 wherein the deviation reduction factor is less than or equal to 0.1.

Claim 16

The clock circuit of claim 10 wherein: a. the generating means comprises an LRC band filter, having an input coupled to receive the majority decision signal; and b. the output means comprises a buffer at an output of the LCR band filter.

Claim 17

The clock circuit of claim 10 wherein: a. the means for generating includes a crystal having a first connection coupled with an output of the determining means; and b. the output means comprises a second, buffered connection of the crystal.

Claim 18

The clock circuit of claim 14 wherein the output means further comprises: a. a capacitor; b. a feedback element; c. a buffer having an input at the second connection of the crystal and an output and which the local signal is supplied; d. a voltage divider coupled with the second connection of the crystal, the voltage divider having a first side for coupling to a first potential, and a second side for coupling via the capacitor to a second potential and for coupling via the feedback element of the output of the buffer.

Claim 19

The clock circuit of claim 10 wherein: a. said output means is an output line; b. the generating means comprises: i. a buffer element having an output connected to said output line; ii. a crystal unit comprising A. a first connection directly connected to the output line; B. a second connection connected to said output line via the buffer element; C. a variable capacitor coupled between the first and second connections; iii. a difference determining device having a first input coupled to the output line and and a second input coupled to receive the majority signal and having an output; iv. an integrator element coupled to the output of the difference determining device and to a control input of the variable capacitor, so that the difference determining means controls the variable capacitor via the integrator element.

Claim 20

The clock circuit of claim 10 wherein: a. the output means comprises a buffer element having an output at which the local clock signal is supplied; and b. the generating means comprises a phase-locked loop which comprises: i. a controlled oscillator, having an output coupled to an input of the buffer element and having an input; ii. a multiplier element, having a first input coupled to the output of the controlled oscillator, a second input coupled to receive the majority signal, and an output; and iii. a low-pass filter having an input coupled with the output of the multiplier element and an output coupled with the input of the controlled oscillator.