Cache memory circuit for processing a read request during transfer of a data block

Claim 1

A cache memory circuit operated in cooperation with a main memory to fetch a data block from said main memory in response to a read request followed by a next read request, said data block being divisible into a sequence of sub-blocks each of which is composed of a plurality of data units successively transferred from said main memory, each of said data units being transferred from said main memory to said cache memory at each transfer timing, said cache memory circuit comprising a cache memory for memorizing said data block, comprising: buffering means coupled to said cache memory for successively buffering said data units transferred from said main memory, to form said sub-block of a plurality of the data units that is to be written into said cache memory for each write-in duration followed by an idle time during which said cache memory is accessible by said next read request; monitoring means coupled to said buffering means for monitoring each sub-block of the block which is being block transferred into said cache memory; said monitoring means including first indicating means for indicating each sub-block of the block that is written into said cache memory and placed in an available status and second indicating means for indicating data availability of said each sub-block that is placed in said available status in the cache memory for the next read request during said idle time; and processing means coupled to said monitoring means and said cache memory for processing the next read request in response to said data availability to read, out of said cache memory, the data unit in said block which is being block transferred.