Associative memory cells

Claim 1

An associative memory cell comprising: a first MOS transistor of a first conductive type; a pair of bit lines, said first transistor connected to one of said bit lines at a first terminal thereof; a word line conductively controlling said first transistor by applying a potential to a second terminal thereof; a second MOS transistor of said first conductive type connected to said second bit line at one terminal thereof and conductively controlled by the potential of the word line applied to a second terminal thereof; an information hold circuit connected between a third terminal of each of said first and second MOS transistors, said information hold circuit storing information received from said first and second transistors; an information retrieval circuit having first and second pairs of MOS transistors of a second conductive type opposite to said first conductive type, said first pair of transistors connected in series at their gate terminals between one terminal of said information hold circuit and one of said bit lines and said second pair of transistors connected in series at their gate terminals between the other terminal of said information hold circuit and said other bit line; and a match line coupled to output terminals of said information retrieval circuit and prechanged in advance of interrogation of a match to maintain a first potential level of the prechanged condition of said match line when a match occurs between the information applied to a bit line and the stored information and to change said first potential level when such a match does not occur.