Nonvolatile random access memory cell

Claim 2

A nonvolatile random access memory (NOVRAM) formed on a semiconductive medium, comprising: two sets of series connected devices, each set comprising a load, a latch transistor of one conductivity-type having a control electrode, and a node connected to said latch transistor and to said load, each set being connected between two voltage supply lines, said node being connected to the control electrode of the latch transistor of the opposite set; and two groups of series connected elements connected between a power line and a respective one of said nodes, said elements in each group comprising an isolation switch and a variable threshold voltage transistor having a floating electrode with means permitting charge tunneling between said floating electrode and one of said nodes.

Claim 3

The NOVRAM of claim 1, wherein said load comprises a load transistor of the opposite conductivity type including a load transistor control electrode.

Claim 4

The NOVRAM of claim 2 wherein said load transistor control electrode is connected directly to the latch transistor control electrode which is in the same set.

Claim 5

The NOVRAM of claim 1 wherein said load comprises a load transistor of said one conductivity type.

Claim 6

The NOVRAM of claim 1 wherein said tunneling means permits charge tunneling between said floating electrode and the opposite one of said nodes.

Claim 7

The NOVRAM of claim 1 wherein said isolation switch of each of said groups comprises a transistor having a control gate connected to the corresponding control gate of the other group.

Claim 8

The NOVRAM of claim 6, wherein said isolation switch of each of said groups comprises a source and a drain, and wherein said isolation switch shares in common with the isolation switch of the other group said control gate and one of said source and drain, the other of said source and drain being connected to the corresponding variable threshold transistor.

Claim 9

The NOVRAM of claim 1 wherein said floating gate is capacitively coupled to the latch transistor control electrode of the same set.

Claim 10

A nonvolatile random access memory (NOVRAM) including variable threshold voltage metal oxide semiconductor (VTVMOS) transistors, comprising: a first branch comprising a first p-channel transistor and a first n-channel transistor, each first transistor comprising a gate, a source and a drain and being connected together drain to drain at a first node therebetween; a second branch comprising a second p-channel transistor and a second n-channel transistor, each second transistor comprising a gate, a source and a drain and being connected together drain to drain at a second node therebetween, the sources of said first and second p-channel transistors being connected to a high supply line and the sources and said first and second n-channel transistors being connected to a low supply line; a first VTVMOS transistor associated with said first node, said first VTVMOS transistor including a first floating gate and including means for permitting electron tunneling between said first floating gate and said second node; a second VTVMOS transistor associated with said second node, said second VTVMOS transistor including a second floating gate having means permitting electron tunneling between said second floating gate and said first node; a first isolation transistor having a gate and being connected in series with said first VTVMOS transistor and one of said supply lines; a second isolation transistor having a gate and being connected in series with said second VTVMOS transistor and said one supply line, the gates of said first and second isolation transistors being connected together; and means connecting between said second node and said first p-channel and n-channel transistor gates, and means connecting between said first node and said second p-channel and n-channel transistor gates.

Claim 11

A nonvolatile random access memory (NOVRAM) including variable threshold voltage metal oxide semiconductor (VTVMOS) transistors, comprising: a first branch comprising a first p-channel transistor and a first n-channel transistor, each first transistor comprising a gate, a source and a drain and being connected together drain to drain at a first node therebetween; a second branch comprising a second p-channel transistor and a second n-channel transistor, each second transistor comprising a gate, a source and a drain and being connected together drain to drain at a second node therebetween, the sources of said first and second p-channel transistors being connected to a high supply line and the sources and said first and second n-channel transistors being connected to a low supply line; a first VTVMOS transistor associated with said first node, said first VTVMOS transistor including a first floating gate and including means for permitting electron tunneling between said first floating gate and said second node; a second VTVMOS transistor associated with said second node, said second VTVMOS transistor including a second floating gate having means permitting electron tunneling between said second floating gate and said first node; a first isolation transistor having a gate and being connected in series with said first VTVMOS transistor and one of said supply lines; a second isolation transistor having a gate and being connected in series with said second VTVMOS transistor and said one supply line, the gates of said first and second isolation transistors being connected together; and means connecting between said second node and said first p-channel and n-channel transistor gates, and means connecting between said first node and said second p-channel and n-channel transistor gates.

Claim 12

The NOVRAM cell of claim 9 further comprising means for applying a restore signal to said first and second isolation transistor gates and bringing said high and low supply lines to the same voltage.

Claim 13

The NOVRAM cell of claim 9 further including an addressing transistor pair connected individually to said first and second nodes and to a bit line and a bit line respectively, said addressing transistor pair each having a gate connected together to a word line.

Claim 14

Th NOVRAM of claim 11 further comprising means for performing a restore operation by forcing said bit and bit lines to the same voltage, turning on said addressing transistor pair and bringing said low and high supply lines to the same voltage.

Claim 15

The NOVRAM of claim 9 further comprising means for bringing said high and low supply lines and said first and second nodes to the same voltage.