Patent US4829422A successfully refreshed from Google Patents.
US4829422A
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Control of multiple processors executing in parallel regions
Assignee: Stardent Computer Inc
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Filing: 1987-04-02
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Granted: 1989-05-09
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Expires: 2007-04-02
Abstract
Abstract Multiple processors are enabled to regulate their work within sections of a machine instruction sequence by storing status information about the state of execution of the parallel regions by the processors, and including, in the machine instruction sequence, parallel control instructions which enable each processor to proceed from section to section on the basis of the status information, without interrupting the execution of the machine instruction sequence.
Inventors
- 👤 Milton A. Morton
- 👤 Peter A. Darnell
- 👤 Lee W. Cooprider
- 👤 Gary Bray
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 16:19
CPC Classifications
G; G06; G06F; G06F8/00; G06F8/40; G06F8/41; G06F8/45; G06F9/00; G06F9/06; G06F9/30; G06F9/30003; G06F9/30076; G06F9/3009; G06F9/30098; G06F9/3012; G06F9/30138
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
83 words
A computer system comprising a plurality of processors working within sections of a stored machine instruction sequence, and storage containing said machine instruction sequence including parallel control instructions which are of a kind and have such locations in the instruction sequence that, when executed by said processors, enable each one of said processors to proceed from section to section based on status information about a state of execution of said sections by said processors, without interrupting the execution of said machine instruction sequence.
Claim 2
Dependent Claim
83 words
A computer system comprising a plurality of processors working within sections of a stored machine instruction sequence, and storage containing said machine instruction sequence including parallel control instructions which are of a kind and have such locations in the instruction sequence that, when executed by said processors, enable each one of said processors to proceed from section to section based on status information about a state of execution of said sections by said processors, without interrupting the execution of said machine instruction sequence.
Claim 3
Dependent Claim
26 words
The system of claim 1 wherein said sections are parallel regions, and said status information is held in storage that is shared by said multiple processors.
Claim 4
Dependent Claim
62 words
The system of claim 1 wherein said status information includes a flag indicating when a region has been completely executed, and said parallel control instructions cause a processor which is a most recent processor to leave said region upon its completion to set said flag, and prevent said processors from thereafter entering said region as a result of their consulting said flag.
Claim 5
Dependent Claim
120 words
The system of claim 2 wherein each one of said parallel regions includes independent blocks that can be executed respectively by different processors such that conflicts between said processors executing said blocks are precluded as a result of consulting information stored in one of a plurality of register sets assigned in common to said processors, said status information includes a value that indicates which register set has been assigned to processors executing in a parallel region, and said parallel control instructions cause each processor, when entering said parallel region, to assign to itself a register set that is the same as a register set assigned to other processors executing within said parallel region, based on said register set indicator value.
Claim 6
Dependent Claim
37 words
The system of claim 1 wherein said status information includes the number of said processors that are actively executing within each said section, and said number is incremented and decremented by processors entering and leaving said section.
Claim 7
Dependent Claim
23 words
The system of claim 2 wherein said status information includes a parallel region descriptor for each parallel region in said machine instruction sequence.
Claim 8
Dependent Claim
104 words
The system of claim 2 wherein each one of said parallel regions includes independent blocks that can be executed respectively by different processors such that conflicts between said processors executing said blocks are precluded as a result of consulting information stored in a resister set assigned in common to said processors, and wherein when all said processors have temporarily left a parallel region before execution of said parallel region is completed, the information in said resistor set is temporarily stored as part of said status information in said shared storage, and is reloaded in said resister set when execution of said parallel region resumes.
Claim 9
Dependent Claim
14 words
The system of claim 1 wherein said machine instruction sequence is any arbitrary sequence.
Claim 10
Dependent Claim
37 words
The system of claim 2 wherein said parallel control instructions include an enter parallel region instruction at a beginning of each one of said parallel regions that is executed by each processor that reaches said parallel region.
Claim 11
Dependent Claim
46 words
The system of claim 2 wherein said parallel region control instructions include an exit parallel region instruction at an end of each one of said parallel regions that is executed by each processor that leaves the parallel region after completing a block in said parallel region.
Claim 12
Independent Claim
70 words
A method for enabling multiple processors to regulate their work within sections of a stored machine instruction sequence, comprising storing status information about a state of execution of said sections by said processors, and including, in the machine instruction sequence, parallel control instructions which enable each one of said processors to proceed from section to section based on said status information without interrupting the execution of said machine instruction sequence.
Claim 13
Independent Claim
70 words
A method for enabling multiple processors to regulate their work within sections of a stored machine instruction sequence, comprising storing status information about a state of execution of said sections by said processors, and including, in the machine instruction sequence, parallel control instructions which enable each one of said processors to proceed from section to section based on said status information without interrupting the execution of said machine instruction sequence.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-08 | 1992-11-07 | 1993-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-08 | 1996-11-07 | 1997-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-08 | 2000-11-07 | 2001-05-09 | $7700.00 | Window Closed / Lapsed |