Patent US4825274A successfully refreshed from Google Patents.
US4825274A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bi-CMOS semiconductor device immune to latch-up
Assignee: Hitachi Ltd
•
Filing: 1986-11-13
•
Granted: 1989-04-25
•
Expires: 2006-11-13
Abstract
Abstract A circuit including a Bi-CMOS semiconductor device of a structure capable of preventing the latch-up phenomenon from occurring when operated as an inverter or the like. The semiconductor device includes a MOS FET and a bipolar transistor merged with each other and having a PNPN or NPNP structure in a region to which minority carriers can migrate through diffusion and in which a same potential is applied to at least a pair of P-type and N-type regions or a backward voltage is applied across PN junctions in operation. The semiconductor device comprises electrodes provided in both P-type and N-type regions, respectively, which form one of the PN junctions, wherein a backward voltage not lower than 0.5 V is applied across the electrodes upon operating the device.
Inventors
- 👤 Hisayuki Higuchi
- 👤 Makoto Suzuki
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 06:49
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0191; H10D84/40; H10D84/401
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
106 words
A semiconductor device including a combination circuit of a bipolar transistor and a MOSFET; wherein said MOSFET includes a gate which responds to an input signal, a source region, a drain region, and a source-drain path; said bipolar transistor includes a collector region connected at one end to a first terminal and at a second end to the source-drain path, a base region connected to the source-drain path, and an emitter region connected to a second terminal, wherein the emitter region, base region and collector region of said bipolar transistor and the source region and drain region of said MOSFET are formed within a semiconductor material.
Claim 2
Dependent Claim
106 words
A semiconductor device including a combination circuit of a bipolar transistor and a MOSFET; wherein said MOSFET includes a gate which responds to an input signal, a source region, a drain region, and a source-drain path; said bipolar transistor includes a collector region connected at one end to a first terminal and at a second end to the source-drain path, a base region connected to the source-drain path, and an emitter region connected to a second terminal, wherein the emitter region, base region and collector region of said bipolar transistor and the source region and drain region of said MOSFET are formed within a semiconductor material.
Claim 3
Dependent Claim
16 words
A semiconductor device according to claim 1, wherein said bipolar transistor is an NPN-type bipolar transistor.
Claim 4
Dependent Claim
15 words
A semiconductor device according to claim 2, wherein said MOSFET is a P-channel type MOSFET.
Claim 5
Dependent Claim
120 words
A semiconductor device including a combination circuit of a bipolar transistor and a MOSFET; wherein said MOSFET includes a gate which responds to an input signal, a source region, a drain region, and a source-drain path; said bipolar transistor includes a collector region connected at one end to a first terminal and at a second end to the source-drain path, a base region connected to the source-drain path, and an emitter region connected to a second terminal, wherein the emitter region, base region and collector region of said bipolar transistor are formed within a first region of a semiconductor material, and the source region and drain region of said MOSFET are formed within a second region of said semiconductor material.
Claim 6
Dependent Claim
120 words
A semiconductor device including a combination circuit of a bipolar transistor and a MOSFET; wherein said MOSFET includes a gate which responds to an input signal, a source region, a drain region, and a source-drain path; said bipolar transistor includes a collector region connected at one end to a first terminal and at a second end to the source-drain path, a base region connected to the source-drain path, and an emitter region connected to a second terminal, wherein the emitter region, base region and collector region of said bipolar transistor are formed within a first region of a semiconductor material, and the source region and drain region of said MOSFET are formed within a second region of said semiconductor material.
Claim 7
Dependent Claim
16 words
A semiconductor device according to claim 4, wherein said bipolar transistor is an NPN-type bipolar transistor.
Claim 8
Dependent Claim
15 words
A semiconductor device according to claim 5, wherein said MOSFET is a P-channel type MOSFET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-24 | 1992-10-24 | 1993-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-24 | 1996-10-24 | 1997-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-24 | 2000-10-24 | 2001-04-25 | $7700.00 | Window Closed / Lapsed |