Semiconductor integrated circuit device

Claim 2

A basic cell formed on a substrate for constituting semiconductor integrated circuit devices, and comprising at least one first MOS transistor of a first type of electric conduction and at least one second MOS transistor of a second type of electric conduction, each of said MOS transistors having a region for constituting a source or drain and a gate electrode, said basic cell characterized by incorporating, in combination: diffusion contact regions of said second type of electric conduction formed on said substrate and disposed on both sides of said region of said first MOS transistor; diffusion contact regions of said first type of electric conduction formed on said substrate and disposed on both sides of said region of said second MOS transistor; said first MOS transistor gate electrode having gate electrode contact regions disposed on both sides of each of said diffusion contact regions of said second type of electric conduction; said first MOS transistor gate electrode contact regions for providing electrical contact with the gate electrode and of a width greater than the width of the gate electrode that bridges each diffusion contact region of second type of electric conduction; said second MOS transistor gate electrode having gate electrode contact regions disposed on both sides of each of said diffusion contact regions of said first type of electric conduction; said second MOS transistor gate electrode contact regions for providing electrical contact with the gate electrode and of a width greater than the width of the gate electrode that bridges each diffusion contact region of first type of electric conduction.

Claim 3

A basic cell as claimed in claim 1 wherein said first and second MOS transistors are respectively symmetrical with respect to the transverse axis running through the center of said region of each said MOS transistor.

Claim 4

A basic cell as claimed in claim 2 wherein said first type of electric conduction is a p-type, and said second type of electric conduction is an n-type.

Claim 5

A semiconductor integrated circuit device of a master slice type including a plurality of basic cells formed on a substrate at regular intervals, characterized in that each of said basic cells comprises: at least one first MOS transistor of a first type of electric conduction having a first region for constituting a source or drain and a first gate electrode; at least one second MOS transistor of a second type of electric conduction having a second region for constituting a source or drain and a first gate electrode; diffusion contact regions of said second type of electric conduction formed on said substrate and disposed on both sides of said first region of said first MOS transistor; diffusion contact regions of said first type of electric conduction formed on said substrate and disposed on both sides of said second region of said second MOS transistor; said first gate electrode having contact regions disposed on both sides of said diffusion contact regions of said second type of electric conduction, said first gate electrode contact regions for providing electrical contact with the first gate electrode and of a width greater than the width of the first gate electrode that bridges each diffusion contact region of second type of electric conduction; said second gate electrode having contact regions disposed on both sides of said diffusion contact regions of said first type of electric conduction; said second gate electrode contact regions for providing electrical contact with the second gate electrode and of a width greater than the width of the second gate electrode that bridges each diffusion contact region of first type of electric conduction.

Claim 6

A semiconductor integrated circuit device of a master slice type including a plurality of basic cells formed on a substrate at regular intervals, characterized in that each of said basic cells comprises: at least one first MOS transistor of a first type of electric conduction having a first region for constituting a source or drain and a first gate electrode; at least one second MOS transistor of a second type of electric conduction having a second region for constituting a source or drain and a first gate electrode; diffusion contact regions of said second type of electric conduction formed on said substrate and disposed on both sides of said first region of said first MOS transistor; diffusion contact regions of said first type of electric conduction formed on said substrate and disposed on both sides of said second region of said second MOS transistor; said first gate electrode having contact regions disposed on both sides of said diffusion contact regions of said second type of electric conduction, said first gate electrode contact regions for providing electrical contact with the first gate electrode and of a width greater than the width of the first gate electrode that bridges each diffusion contact region of second type of electric conduction; said second gate electrode having contact regions disposed on both sides of said diffusion contact regions of said first type of electric conduction; said second gate electrode contact regions for providing electrical contact with the second gate electrode and of a width greater than the width of the second gate electrode that bridges each diffusion contact region of first type of electric conduction.

Claim 7

A semiconductor integrated circuit device as claimed in claim 4 wherein said first MOS transistor is symmetrical with respect to the transverse axis running through the center of said first region and wherein said second MOS transistor is symmetrical with respect to the transverse axis running through the center of said second region.

Claim 8

A semiconductor integrated circuit device as claimed in claim 5 wherein said first type of electric conduction is a p-type and said second type of electric conduction is an n-type.

Claim 9

A semiconductor integrated circuit device as claimed in any one of claims 4-6 wherein said plurality of basic cells are arranged such as to form a plurality of rows of basic cells.

Claim 10

A semiconductor integrated circuit device as claimed in claim 7 wherein said plurality of rows of basic cells include pairs of the adjacent two rows of basic cells, and wherein the arrangement of the MOS transistors in each cell in one of said adjacent two rows is interchanged with that of the MOS transistors of each basic cell in the other of said adjacent two rows with respect to the center line of the area sandwiched between said adjacent two rows.

Claim 11

A basic cell as claimed in claim 1 having a longitudinal cell axis common to both said first and second MOS transistors, each said MOS transistor region including a source/drain region, said diffusion contact regions of said second type of electric conduction including a pair of diffusion contact regions spacedly disposed along said cell axis on opposite respective sides of said source/drain region of said first MOS transistor, said diffusion contact regions of said first type of electric conduction including a pair of diffusion contact regions spacedly disposed along said cell axis on opposite respective sides of said source/drain region of said second MOS transistor.

Claim 12

A basic cell as claimed in claim 9 wherein the gate electrode contact regions of said first MOS transistor include two pairs of gate electrode contact regions, disposed spacedly along said cell axis, each pair disposed on opposite sides of each of said diffusion contact regions of said second type of electric conduction, the gate electrode contact regions of said second MOS transistor including two pairs of gate electrode contact regions disposed spacedly along said cell axis, each pair disposed on opposite sides of each of said diffusion contact regions of said first type of electric conduction.

Claim 13

A semiconductor integrated circuit device as claimed in claim 4, having a longitudinal cell axis common to both said first and second MOS transistors, each said MOS transistor region including a source/drain region, said diffusion contact regions of said second type of electric conduction including a pair of diffusion contact regions spacedly disposed along said cell axis on opposite respective sides of said source/drain region of said first MOS transistor, said diffusion contact regions of said first type of electric conduction including a pair of diffusion contact regions spacedly disposed along said cell axis on opposite respective sides of said source/drain region of said second MOS transistor.

Claim 14

A semiconductor integrated circuit device as claimed in claim 11 wherein the gate electrode contact regions of said first MOS transistor include two pairs of gate electrode contact regions, disposed spacedly along said cell axis, each pair disposed on opposite sides of each of said diffusion contact regions of said second type of electric conduction, the gate electrode contact regions of said second MOS transistor including two pairs of gate electrode contact regions disposed spacedly along said cell axis, each pair disposed on opposite sides of each of said diffusion contact regions of said first type of electric conduction.