EP0177336A2
Expired / Lapsed
EP
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Gate array integrated device
Assignee: Fujitsu Ltd
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Filing: 1985-10-01
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Granted: —
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Expires: 2005-10-01
Abstract
Abstract A gate array integrated device incuding a plurality of single column type arrays (BC1), a plurality of matrix type arrays such as double column type arrays (BC2), and longitudinal connection areas (CH) provided between the arrays (BC1, BC2). One of the single column type arrays faces at least one side of each of the matrix type arrays (BC2).
Inventors
- 👤 Yoshihisa Takayama
- 👤 Kazuyuki Kawauchi
- 👤 Shigeru Fujii
- 👤 Toshihiko Yoshida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/90; H10D84/903; H10D84/907; H10B; H10B41/00; H10B41/30; H10B41/35; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D89/00; H10D89/10; H10D89/211; H10D89/213; H10W; H10W20/00; H10W20/40; H10W20/41; H10W20/43
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
176 words
A gate array integrated device comprising a plurality of single column type arrays (BC1) each comprising a series of basic cells arranged along the column direction of said device; a plurality of matrix type arrays (BC2, BC4) each comprising a plurality of column arrays in proximity to each other along the row direction of said device, each of said column arrays comprising a series of basic cells arranged along the column direction of said device; a plurality of first power supply lines (LA 1 LA 2 ' ...) arranged along the column direction of said device over said single column type arrays (BC1) said matrix type arrays (BC2, BC4); and longitudinal connection areas (CH), arranged along the column direction of said device between said single column type arrays (BC1) and said matrix type arrays (BC2, BC4), for providing areas of connections for connecting said basic cells to each other, thereby creating unit cells, one of said single column type arrays (BC1) facing toward at least one side of each of said matrix type arrays (BC2, BC4).
Claim 2
Dependent Claim
176 words
A gate array integrated device comprising a plurality of single column type arrays (BC1) each comprising a series of basic cells arranged along the column direction of said device; a plurality of matrix type arrays (BC2, BC4) each comprising a plurality of column arrays in proximity to each other along the row direction of said device, each of said column arrays comprising a series of basic cells arranged along the column direction of said device; a plurality of first power supply lines (LA 1 LA 2 ' ...) arranged along the column direction of said device over said single column type arrays (BC1) said matrix type arrays (BC2, BC4); and longitudinal connection areas (CH), arranged along the column direction of said device between said single column type arrays (BC1) and said matrix type arrays (BC2, BC4), for providing areas of connections for connecting said basic cells to each other, thereby creating unit cells, one of said single column type arrays (BC1) facing toward at least one side of each of said matrix type arrays (BC2, BC4).
Claim 3
Dependent Claim
20 words
A device as set forth in claim 1, wherein each of said basic cells comprises P-channel transistors and N-channel transistors.
Claim 4
Dependent Claim
42 words
A device as set forth in claim 2, wherein one column array and its adjacent column array within one of said matrix type arrays have an "image by inversion" relationship to each other regarding the arrangement of said P-channel and N-channel transistors.
Claim 5
Dependent Claim
213 words
A device as set forth in claim 1, 2 or 3, further comprising: traverse connection areas (CH') arranged along the row direction of said device between the basic cells of said single column type arrays (BC1) and said matrix type arrays (BC2, BC4); impurity diffusion regions (R 1 , R 2 ), formed on said traverse connection areas crossing said single column type arrays (BC1), for providing a substrate bias thereto; a plurality of second power supply lines (LB) arranged on said traverse connection areas (CH I ); when a clip operation is required for clipping one gate of said basic cells of said single column type arrays to a desired potential and a power supply line having said desired potential is located at the traverse connection area adjacent to said gate, means for clipping said gate to said power supply line having said desired potential; and when a clip operation is required for clipping one gate of said basic cells of said single column type arrays to a desired potential and no power supply line having said desired potential is located at the traverse connection area adjacent to said gate, means for clipping said gate to one of said impurity diffusion regions formed in the traverse connection area adjacent to said gate.
Claim 6
Dependent Claim
43 words
A device as set forth in claim 4, further comprising a plurality of third power supply lines (LC 1 , LC 2 , ...) each arranged over and connected to one of said first power supply lines (LA 1 , LA2 , ...).
Claim 7
Dependent Claim
36 words
A device as set forth in claim 5, wherein said third power supply lines (LC 1 , LC 2 , ...) are wider than said first power supply lines (LA 1 , LA 2 , ...).
Claim 8
Independent Claim
213 words
A device as set forth in any claim, further comprising: traverse connection areas (CH') arranged along the row direction of said device between the basic cells of said single column type arrays (BC1) and said matrix type arrays (BC2, BC4); impurity diffusion regions (R 1 , R4), formed on said traverse connection areas crossing said matrix column type arrays (BC2, BC4), for providing a substrate bias thereto; a plurality of second power supply lines (LB) arranged on said traverse connection areas (CH'); when a clip operation is required for clipping one gate of an inside one of said basic cells of said matrix type arrays to a desired potential and a power supply line having said desired potential is located at the traverse connection area adjacent to said gate, means for clipping said gate to said power supply line having said desired potential; and when a clip operation is required for clipping one gate of an inside one of said basic cells of said matrix type arrays to a desired potential and no power supply line having said desired potential is located at the traverse connection area adjacent to said gate, means for clipping said gate to one of said impurity diffusion regions formed in the traverse connection area adjacent to said gate.
Claim 9
Dependent Claim
44 words
A device as set forth in claim 7, further comprising a plurality of third power supply lines (LC 1 , LC 2 , ...) each arranged over and connected to one of said first power supply lines (LA 1 , LA 2 , ...).
Claim 10
Dependent Claim
36 words
A device as set forth in claim 8, wherein said third power supply lines (LC 1 , LC 2 , ...) are wider than said first power supply lines (LA 1 , LA 2 ' ...).
References Cited (Backward Citations)
No citation records indexed.
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