EP0136880A1
Expired / Lapsed
EP
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Gate array type semiconductor integrated circuit device
Assignee: Fujitsu Ltd
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Filing: 1984-09-26
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Granted: —
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Expires: 2004-09-26
Abstract
Abstract A gate array type semiconductor device including a plurality of basic cells (11) arranged in an array and diffusion regions (18, 19) for suppressing latchup between the basic cells (11) In the array has each of the diffusion regions (18, 19) formed as a comb-shaped structure. The teeth (18c, 19c) of the structures (18, 19) extend between the basic cells (11) in each column and occupy less space than the conventional diffusion regions (14,15) (Figure 5) since ohmic contacts are no longer required between every pair of adjacent basic cells. The comb-shaped diffusion regions (18, 19) partially enclose each basic cell (11).
Inventors
- 👤 Yoshihisa Takayama
- 👤 Shigeru Fujii
- 👤 Tomoaki Tanabe
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 09:02
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854; H10D84/01; H10D84/02; H10D84/03; H10D84/038; H10D84/90; H10D84/903; H10D84/907
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
217 words
A gate array type of semiconductor integrated circuit device formed in a semiconductor substrate (10), comprising an array of basic cells (11) arranged in columns and rows with column spaces (13) between adjacent columns and row spaces (12) between adjacent rows, each of the basic cells (11) including a first-channel MIS transistor (TR,, TR 2 ) formed in the silicon substrate (10) of one conductivity type and a second-channel MIS transistor (TR 3 , TR 4 ) formed in a well (9) of other conductivity type; a plurality of first diffusion regions (15) of one conductivity type in contact with the semiconductor substrate (10) and located in the row spaces (12) between adjacent basic cells (11) the first diffusion regions (15) being ohmically connected with a first power line (VDD), and a plurality of second diffusion regions (14) of the other conductivity type in contact with the wells (9) and located in the row spaces (12) between adjacent basic cells (11), the second diffusion regions (14) being ohmically connected with a second power line (V SS ) , characterised in that both the first (18) and second (19) diffusion regions have a comb-shaped structure arranged with its base (18a, 19a) along the column spaces (13) and its teeth (18b, c, 19b, c) along the row spaces (12).
Claim 2
Dependent Claim
217 words
A gate array type of semiconductor integrated circuit device formed in a semiconductor substrate (10), comprising an array of basic cells (11) arranged in columns and rows with column spaces (13) between adjacent columns and row spaces (12) between adjacent rows, each of the basic cells (11) including a first-channel MIS transistor (TR,, TR 2 ) formed in the silicon substrate (10) of one conductivity type and a second-channel MIS transistor (TR 3 , TR 4 ) formed in a well (9) of other conductivity type; a plurality of first diffusion regions (15) of one conductivity type in contact with the semiconductor substrate (10) and located in the row spaces (12) between adjacent basic cells (11) the first diffusion regions (15) being ohmically connected with a first power line (VDD), and a plurality of second diffusion regions (14) of the other conductivity type in contact with the wells (9) and located in the row spaces (12) between adjacent basic cells (11), the second diffusion regions (14) being ohmically connected with a second power line (V SS ) , characterised in that both the first (18) and second (19) diffusion regions have a comb-shaped structure arranged with its base (18a, 19a) along the column spaces (13) and its teeth (18b, c, 19b, c) along the row spaces (12).
Claim 3
Dependent Claim
55 words
A gate array device according to claim 1, wherein each comb-shaped first (18) and second (19) diffusion region includes wide teeth (18b, 19b) and narrow teeth (18c, 19c) formed as an integral structure, ohmic contacts between the regions (18, 19) and the power lines (V DD' V SS ) being,located only on the wide teeth.
Claim 4
Dependent Claim
74 words
A gate array device according to claim 1, wherein each of the comb-shaped first (18) and second (19) diffusion regions consists of a base part (18a, 19a) formed along the column spaces and narrow teeth (18c, 19c) formed along the row spaces, as an integral structure, the ohmic contacts between the diffusion regions (18, 19) and the power lines (V DD , V SS ) being formed only in the base parts (18a, 19a).
Claim 5
Dependent Claim
30 words
A gate array device according to claim 2 or 3, wherein each said narrow tooth part has a minimum width among the circuit elements fabricated in the same semiconductor substrate.
References Cited (Backward Citations)
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