EP0009782A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
CMOS Semiconductor device
Assignee: Toshiba Corp
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Filing: 1979-09-28
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Granted: —
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Expires: 1999-09-28
Abstract
Abstract A complementary type MOS transistor device is disclosed including a p-channel type MOS transistor having source, drain and gate regions (10, 12, 20) formed in the n-well region (6) which is formed in the surface area of a p-type semiconductor layer (4) and an n-channel MOS transistor having source, drain and gate regions (13, 14, 22) formed in said semiconductor layer (4). The semiconductor layer (4) is formed on an n-type semi-conductor body (2) and a reverse bias voltage is applied between the semiconductor layer (4) and the semiconductor substrate (2).
Inventors
- 👤 Yukimasa Uchida
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 12:10
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/85; H10D84/854
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
142 words
A semiconductor device having a semiconductor layer (4) of a first conductivity type, a well region (6) of a second conductivity type opposite to the first conductivity type,first and second semiconductor regions (13,14) of the second conductivity type formed in the surface area of said semiconductor layer, third and fourth semiconductor regions (10, 12) of the first conductivity type formed in the surface area of said well region, a first gate electrode (22) insulatively arranged on that surface area of said semiconductor layer (4) which lies between said first and second semiconductor regions (13, 14), and a second gate electrode (20) insulatively arranged on that surface area of said well region (6) which lies between said third and fourth semiconductor regions (10, 12), characterized in that said semiconductor layer (4) is formed on a semiconductor substrate (2) of the second conductivity type.
Claim 2
Dependent Claim
142 words
A semiconductor device having a semiconductor layer (4) of a first conductivity type, a well region (6) of a second conductivity type opposite to the first conductivity type,first and second semiconductor regions (13,14) of the second conductivity type formed in the surface area of said semiconductor layer, third and fourth semiconductor regions (10, 12) of the first conductivity type formed in the surface area of said well region, a first gate electrode (22) insulatively arranged on that surface area of said semiconductor layer (4) which lies between said first and second semiconductor regions (13, 14), and a second gate electrode (20) insulatively arranged on that surface area of said well region (6) which lies between said third and fourth semiconductor regions (10, 12), characterized in that said semiconductor layer (4) is formed on a semiconductor substrate (2) of the second conductivity type.
Claim 3
Dependent Claim
28 words
A semiconductor device according to claim 1, characterized in that a reverse bias voltage (VB ) is applied between said semiconductor layer (4) and said semiconductor substrate (2).
Claim 4
Dependent Claim
43 words
A semiconductor device according to claim 1 or 2, characterized by further comprising a fifth semiconductor region (26) of the second conductivity type formed in the surface area of said semiconductor layer (4) to which an reverse bias voltage (VB ) is applied.
Claim 5
Dependent Claim
31 words
A semiconductor device according to claim 3, characterized in that said fifth semiconductor region (26) is arranged between said well region (6), and said first and second semiconductor regions (13, 14).
Claim 6
Dependent Claim
30 words
A semiconductor device according to claim 3, characterized in that said fifth semiconductor region (26) is kept at the same voltage (VB ) as that of said semiconductor substrate (2).
References Cited (Backward Citations)
FR1567602A
Cited
US4053925A
Cited
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