Patent US4823030A successfully refreshed from Google Patents.
US4823030A
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Ecl logic gate using multi-emitter transistors
Assignee: Siemens AG
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Filing: 1988-01-06
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Granted: 1989-04-18
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Expires: 2008-01-06
Abstract
Abstract A semiconductor circuit arrangement in ECL technology having logical conjunctions between more than two input variables, includes two series-gating stages having ECL current switches, which are controlled by an input variable, each including a reference circuit and at least one control circuit, at least one threshold voltage diode for separating at least two of the logical junctions from one another, further comprising a multiemitter transistor included in the control circuit of the ECL current switch forming the reference circuit, at least one diode-connected transistor having at least two emitters and one collector resistor which forms a logical conjunction of the signal present at the emitters of the diode-connected transistor.
Inventors
- 👤 Wilhelm Wilhelm
- 👤 Karl-Reinhard Schon
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 21:32
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738; H03K19/08; H03K19/082; H03K19/086; H03K19/0866
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
109 words
A semiconductor circuit for forming logic functions in ECL technology, comprising first and second cascade-connected series-gating stages having respective first and second ECL current switches, said current switches having respective first and second control circuit each being controlled by at least two input variables, said current switches having respective first and second reference circuits connected to its corresponding control circuit, said first reference circuit having a multi-emitter transistor, said first control circuit having at least one diode-connected multi-emitter transistor connected at its collector to a resistor to form preliminary logic output signals as a logic function of the at least two input variables applied to the first control circuit.
Claim 2
Dependent Claim
109 words
A semiconductor circuit for forming logic functions in ECL technology, comprising first and second cascade-connected series-gating stages having respective first and second ECL current switches, said current switches having respective first and second control circuit each being controlled by at least two input variables, said current switches having respective first and second reference circuits connected to its corresponding control circuit, said first reference circuit having a multi-emitter transistor, said first control circuit having at least one diode-connected multi-emitter transistor connected at its collector to a resistor to form preliminary logic output signals as a logic function of the at least two input variables applied to the first control circuit.
Claim 3
Dependent Claim
20 words
Semiconductor circuit according to claim 1, wherein said input variables include addressing signals and data signals and their complementary signals.
Claim 4
Dependent Claim
70 words
Semiconductor circuit according to claim 2, wherein said second series-gating stage comprises a further ECL current switch cascade-connected to said second ECL current switch to form a series circuit across a circuit voltage supply, said second ECL current switch receiving a more positive operation potential than said further ECL current switch to form a highest gating level, and wherein said data signals are applied to drive said highest gating level.
Claim 5
Dependent Claim
24 words
Semiconductor circuit according to claim 2 including emitter followers, wherein the input variables are applied to the respective control circuits via the emitter followers.
Claim 6
Dependent Claim
30 words
Semiconductor circuit according to claim 2, including at least two ECL current switches included in at least one of the series-gating stage, each switch being controlled by an input variable.
Claim 7
Dependent Claim
24 words
Semiconductor circuit according to claim 5, including one of a diode-connected transistor and a diode included in at least one of the control circuits.
Claim 8
Dependent Claim
47 words
Semiconductor circuit according to claim 3, wherein said at least one diode-connected transistor and said collector resistor forms said preliminary logic output signals as a function of the addressing signals, and said addressing, data, and output signals have voltage levels at or below said highest gating level.
Claim 9
Dependent Claim
146 words
Semiconductor circuit according to claim 1 which includes at least a first and a second emitter-follower transistor being connected in series and being controlled by said input variables and said preliminary logic output signals applied to their respective bases, said second emitter-follower transistor being the current source of said first emitter-follower transistor, a control transistor of said second control circuit being connected to a junction point between said first and second emitter-follower transistors; said second series-gating stage having a further ECL current switch cascade-connected to said second ECL current switch, said further ECL current switch having a further control circuit having at least one further control transistor, the collector of said further control transistor being connected to the connected emitters of said transistors of the second ECL-current switch, and the base of said further control transistor being connected to the emitter of said second emitter-follower transistor.
Claim 10
Dependent Claim
36 words
Semiconductor circuit according to claim 8, wherein said preliminary logic output signals are generated by voltage addition at said collector resistor of a further one of said input variables and said at least two input variables.
Claim 11
Dependent Claim
17 words
Semiconductor circuit according to claim 9, including resistors connected for matching voltage levels internally to the circuit.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-04-17 | 1992-10-17 | 1993-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-04-17 | 1996-10-17 | 1997-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-04-17 | 2000-10-17 | 2001-04-18 | $7700.00 | Window Closed / Lapsed |