US4007384A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Noninverting current-mode logic gate
Assignee: AT&T Inc
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Filing: 1975-12-08
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Granted: 1977-02-08
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Expires: 1995-12-08
Abstract
Abstract A high speed bipolar noninverting current-mode logic AND gate is the basic building block for a current-mode logic family. The AND gate comprises a current steering differential pair of transistors, a pair of dual emitter input transistors, a dual emitter reference transistor, an output resistor and a fixed current source. The conducting state of the current steering transistor pair is so controlled that a logic "one" at the base electrodes of both input transistors produces a logic "one" at an output terminal taken from the collector electrode of the reference transistor. Further, a logic "zero" at both input transistors produces a logic "zero" at the output terminal and finally the condition of a "zero" at one input and a "one" at the other input produces a "zero" at the output. This result is attained as a consequence of control of the conduction state of the current steering pair so as to provide the same current level through the reference transistor for the "zero-one" input as for the "zero-zero" input, thus producing the noninverting AND function.
Inventors
- 👤 Richard Donald Brooks
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 19:09
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/086; H03K19/0863; H03K19/0866
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
187 words
A noninverting current-mode logic AND gate comprising, 1. a pair of input terminals, 2. an output terminal, 3. a source of substantially constant current, including a supply terminal adapted for connection to a source of voltage, 4. a pair of differentially-connected, emitter-coupled, current steering transistors connected to said current source, 5. a first input transistor having its base connected to one of said input terminals, 6. a second input transistor having its base connected to the other input terminal, 7. said input transistors having dual emitters, 8. a reference transistor having its collector connected to said output terminal and having dual emitters, 9. first means connecting one emitter of said first input transistor to one emitter of said reference transistor and to the collector of one of said current steering transistors, 10. second means connecting one emitter of said second input transistor to the other emitter of said reference transistor and the other collector of the other of said current steering transistors, 11. third means connecting the other emitter of said first input transistor to the base electrode of the other of said current steering transistors, and
Claim 2
Dependent Claim
187 words
A noninverting current-mode logic AND gate comprising, 1. a pair of input terminals, 2. an output terminal, 3. a source of substantially constant current, including a supply terminal adapted for connection to a source of voltage, 4. a pair of differentially-connected, emitter-coupled, current steering transistors connected to said current source, 5. a first input transistor having its base connected to one of said input terminals, 6. a second input transistor having its base connected to the other input terminal, 7. said input transistors having dual emitters, 8. a reference transistor having its collector connected to said output terminal and having dual emitters, 9. first means connecting one emitter of said first input transistor to one emitter of said reference transistor and to the collector of one of said current steering transistors, 10. second means connecting one emitter of said second input transistor to the other emitter of said reference transistor and the other collector of the other of said current steering transistors, 11. third means connecting the other emitter of said first input transistor to the base electrode of the other of said current steering transistors, and
Claim 3
Dependent Claim
23 words
fourth means connecting the other emitter of said second input transistor to the base electrode of said one of the current steering transistors.
Claim 4
Dependent Claim
23 words
fourth means connecting the other emitter of said second input transistor to the base electrode of said one of the current steering transistors.
Claim 5
Dependent Claim
237 words
A noninverting current-mode logic gate comprising 1. first and second input terminals, 2. first and second output terminals, 3. a source of substantially constant current, including a supply terminal adapted for connection to a source of voltage, 4. a pair of differentially-connected, emitter-coupled current steering transistors connected to said current source, 5. a reference transistor having its collector connected to said second output terminal and having dual emitters, 6. a first input transistor having its base connected to said first input terminal, its collector to said first output terminal and its emitter to one emitter of said reference transistor, 7. a second input transistor having its base connected to said second input terminal, its collector to said first output terminal and its emitter to the other emitter of said reference transistor, 8. a third input transistor having its base connected to said first input terminal and its emitter to the base electrode of one of said current steering transistors, 9. a fourth input transistor having its base connected to said second input terminal and its emitter to the base electrode of the other of said current steering transistors, 10. said third and fourth input transistors having interconnected collector electrodes, 11. means connecting the collector of said one current steering transistor to the emitter of said second input transistor, 12. means connecting the collector of said other current steering transistor to the emitter of said first input transistor.
Claim 6
Dependent Claim
237 words
A noninverting current-mode logic gate comprising 1. first and second input terminals, 2. first and second output terminals, 3. a source of substantially constant current, including a supply terminal adapted for connection to a source of voltage, 4. a pair of differentially-connected, emitter-coupled current steering transistors connected to said current source, 5. a reference transistor having its collector connected to said second output terminal and having dual emitters, 6. a first input transistor having its base connected to said first input terminal, its collector to said first output terminal and its emitter to one emitter of said reference transistor, 7. a second input transistor having its base connected to said second input terminal, its collector to said first output terminal and its emitter to the other emitter of said reference transistor, 8. a third input transistor having its base connected to said first input terminal and its emitter to the base electrode of one of said current steering transistors, 9. a fourth input transistor having its base connected to said second input terminal and its emitter to the base electrode of the other of said current steering transistors, 10. said third and fourth input transistors having interconnected collector electrodes, 11. means connecting the collector of said one current steering transistor to the emitter of said second input transistor, 12. means connecting the collector of said other current steering transistor to the emitter of said first input transistor.
Claim 7
Dependent Claim
56 words
A current-mode logic gate in accordance with claim 2 in which the base electrode of said third input transistor is connected to said second input terminal instead of to said first input terminal and the base electrode of said fourth input transistor is connected to said first input terminal instead of to said second input terminal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-02-08 | 1980-08-09 | 1981-02-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-02-08 | 1984-08-09 | 1985-02-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-02-08 | 1988-08-09 | 1989-02-08 | $7700.00 | Window Closed / Lapsed |