Integrated circuit with improved protective device

Claim 2

A protective device for a functional circuit fabricated on a major surface of a semiconductor substrate of a first conductivity type, comprising first and second regions of a second conductivity type spaced apart from each other and formed at said major surface of said semiconductor substrate, each of said first and second regions having at least a first side and a second side opposite to said first side, the first side of said first region and the first side of said second region facing to each other substantially in parallel and being spaced apart via an isolating area, an insulating layer overlying said major surface of said semiconductor substrate to cover at least said first and second regions, a conductive layer formed on said insulating layer near the second side of said first region, said conductive layer being supplied with an external signal and electrically connected to said first region, a third region of said second conductivity type formed at said major surface of said semiconductor substrate and having at least first and second opposite ends, said third region being connected at its first end to a central part of said second side of said first region and extending therefrom through a region underlying said conductive layer, a wiring layer electrically connected to said second region and supplied with a reference potential, and means for connecting the second end to said third region of said functional circuit.

Claim 3

The protective device according to claim 1, in which a width of said isolating area is about 4 microns or less.

Claim 4

The protective device according to claim 1, in which said conductive layer is connected to said first region through a first polysilicon layer formed over said second side of said first region and said wiring layer is connected to said second region through a second polysilicon layer formed over said second side of said second region opposite to said first side thereof.

Claim 5

The protective device according to claim 1, in which said isolation area is formed of an insulating material.

Claim 6

An integrated circuit comprising a semiconductor substrate of a first conductivity type, a first rectangular region of a second conductivity formed in said substrate and having first and second parallel longitudinal sides, a second rectangular region of said second conductivity type formed in said substrate and having first and second parallel longitudinal sides, the first side of said first rectangular region being spaced apart in parallel, a resistor region of said second conductivity type formed in said substrate, said resistor region being connected to a central part of said second side of said first region, a first insulating layer substantially covering the surface of said first and second rectangular regions and said resistor region, a second insulating layer substantially covering the surface of said semiconductor substrate other than said first and second rectangular regions and said resistor region, said first insulating layer being thinner than said second insulating layer, a first polysilicon layer formed on said first rectangular region in parallel with said second side thereof via said first insulating layer and contacted with said first rectangular region through a contact hole formed in said first insulating layer, a second polysilicon layer formed on said second rectangular region via said first insulating layer in parallel with said second side of said second rectangular region and contacted with said second rectangular region through a contact hole formed in said first insulating layer, a third insulating layer covering said first and second polysilicon layers and said first and second insulating layers, a first aluminum layer formed on said third insulating layer and over a part of said first rectangular region and a part of said resistor region, said first aluminum layer being supplied with an external signal and connected to said first polysilicon layer through a contact hole formed in said third insulating layer, a second aluminum layer formed on said third insulating layer and connected to said second rectangular region through a contact hole formed in said third insulating layer, said second aluminum layer being supplied with a reference potential, a transistor formed in said substrate, and means for connecting a part of said resistor region to said transistor.

Claim 7

An integrated circuit comprising a semiconductor substrate of a first conductivity type, a first rectangular region of a second conductivity formed in said substrate and having first and second parallel longitudinal sides, a second rectangular region of said second conductivity type formed in said substrate and having first and second parallel longitudinal sides, the first side of said first rectangular region being spaced apart in parallel, a resistor region of said second conductivity type formed in said substrate, said resistor region being connected to a central part of said second side of said first region, a first insulating layer substantially covering the surface of said first and second rectangular regions and said resistor region, a second insulating layer substantially covering the surface of said semiconductor substrate other than said first and second rectangular regions and said resistor region, said first insulating layer being thinner than said second insulating layer, a first polysilicon layer formed on said first rectangular region in parallel with said second side thereof via said first insulating layer and contacted with said first rectangular region through a contact hole formed in said first insulating layer, a second polysilicon layer formed on said second rectangular region via said first insulating layer in parallel with said second side of said second rectangular region and contacted with said second rectangular region through a contact hole formed in said first insulating layer, a third insulating layer covering said first and second polysilicon layers and said first and second insulating layers, a first aluminum layer formed on said third insulating layer and over a part of said first rectangular region and a part of said resistor region, said first aluminum layer being supplied with an external signal and connected to said first polysilicon layer through a contact hole formed in said third insulating layer, a second aluminum layer formed on said third insulating layer and connected to said second rectangular region through a contact hole formed in said third insulating layer, said second aluminum layer being supplied with a reference potential, a transistor formed in said substrate, and means for connecting a part of said resistor region to said transistor.

Claim 8

A protective device for a functional circuit fabricated on a major surface of a semiconductor region of a first conductivity type, comprising an insulating layer, a metal input pad formed at said major surface via said insulating layer; a reference voltage wiring supplied with a reference voltage and formed at said major surface via said insulating layer; a punch-through transistor having a channel region, first and second regions of a second conductivity type spaced apart via said channel region, each of said first and second regions having a first side wall facing said channel region and a second side wall opposite to said first side wall, said first region serving one of a drain and a source of said punch-through transistor and said second region serving as the other of said drain and said source, said first region being electrically connected to said metal input pad, and said second region being electrically connected to said reference voltage wiring; a resistor region of said second conductivity type, having first and second ends and being formed in a strip pattern, said first end of said resistor region being directly connected to a central portion of said second side wall of said first region; and means for connecting the second end of said region to said functional circuit.

Claim 9

A protective device for a functional circuit fabricated on a major surface of a semiconductor region of a first conductivity type, comprising an insulating layer, a metal input pad formed at said major surface via said insulating layer; a reference voltage wiring supplied with a reference voltage and formed at said major surface via said insulating layer; a punch-through transistor having a channel region, first and second regions of a second conductivity type spaced apart via said channel region, each of said first and second regions having a first side wall facing said channel region and a second side wall opposite to said first side wall, said first region serving one of a drain and a source of said punch-through transistor and said second region serving as the other of said drain and said source, said first region being electrically connected to said metal input pad, and said second region being electrically connected to said reference voltage wiring; a resistor region of said second conductivity type, having first and second ends and being formed in a strip pattern, said first end of said resistor region being directly connected to a central portion of said second side wall of said first region; and means for connecting the second end of said region to said functional circuit.

Claim 10

The protective device according to claim 6, in which said punch-through transistor has a thick insulating layer formed on said channel region, said thick insulating having a thickness of a range of 3000 angstroms to 9000 angstroms.

Claim 11

The protective device according to claim 6, in which a first polysilicon layer is provided between said metal pad and said first region and a second polysilicon layer is provided between said reference voltage wiring and said second region.