Predecode and multiplex in addressing electrically programmable memory

Claim 2

A one-of-(N×V) decoder formed in a single semiconductorintegrated circuit for addressing N×V rows of a semiconductor memory array or the like within said integrated circuit, comprising: buffer means for receiving M address bits from external to the integrated circuit and producing complements thereof, where 2 M =N×V; a plurality of T predecode means each receiving from said buffer means a subset of R of said M address bits and complements thereof and each producing a one-of-S output, where T is an integer and S=2 R ; and decoder means having N logic circuits with each logic circuit having T inputs, where N×T is much less than N×M; wherein each of said T inputs of said N loic circuits includes a transistor and the total number of such transistors is much less than (N×V)×M; the decoder means producing an output on one-of-N separate output lines; each of the N output lines of the decoder being connected to a one-of-V multiplexer, where V is an integral power of 2, to produce a one-of-(N×V) output to rows of the array, each said multiplexer receiving from said buffer means U address bits and complements thereof, where 2 U =V.

Claim 3

Apparatus for selecting one out of N lines in a semiconductor memory array in response to an address of A bits, where N is a power of 2 greater than 2 5 , said apparatus and memory array both being formed in a single semiconductor integrated circuit, comprising: means for detecting each of said A address bits received from external to said integrated circuit and producing a pair of true and complement address signals for each of said A address bits; means connected to receive the address signals for predecoding the address by converting sets of said pairs of true and complement address signals to sets of one-of-(2 B ) select signals, where B is a small integral power of 2; a plurality of N/M multiplex circuits, where M is a power of 2 no greater than 2 3 ; a one-of-(N/M) decoder; means for applying a first of said sets of select signals to all of said multiplex circuits, each multiplex circuit having M output lines which are part of said N output lines of the array, and means for applying the remaining sets of select signals to inputs of said one-of-(N/M) decoder, the decoder having N/M outputs each connected separately to an input of one of said multiplex circuits, wherein each of said inputs of said one-of-(N/M) decoder includes a transistor, and the number of said inputs is many times smaller than N×A.

Claim 4

Apparatus for selecting one out of N lines in a semiconductor memory array in response to an address of A bits, where N is a power of 2 greater than 2 5 , said apparatus and memory array both being formed in a single semiconductor integrated circuit, comprising: means for detecting each of said A address bits received from external to said integrated circuit and producing a pair of true and complement address signals for each of said A address bits; means connected to receive the address signals for predecoding the address by converting sets of said pairs of true and complement address signals to sets of one-of-(2 B ) select signals, where B is a small integral power of 2; a plurality of N/M multiplex circuits, where M is a power of 2 no greater than 2 3 ; a one-of-(N/M) decoder; means for applying a first of said sets of select signals to all of said multiplex circuits, each multiplex circuit having M output lines which are part of said N output lines of the array, and means for applying the remaining sets of select signals to inputs of said one-of-(N/M) decoder, the decoder having N/M outputs each connected separately to an input of one of said multiplex circuits, wherein each of said inputs of said one-of-(N/M) decoder includes a transistor, and the number of said inputs is many times smaller than N×A.

Claim 5

Apparatus according to claim 2 wherein M=B.

Claim 6

Address decoding circuitry formed in a semiconductor integrated circuit comprising: a first buffer circuit for receiving a first address bit and producing first and second true address voltages of the same logic state at first and second true outputs, first power-down means. connected in series between said first and second true outputs for introducing a voltage differential, said first buffer circuit also producing first and second complement address voltages of the same logic state at first and second complement outputs, second power-down means connected in series between said first and second complement outputs for introducing a voltage differential, a second buffer circuit for receiving a second address bit and producing third and fourth true address voltages of the same logic state at third and fourth true outputs, third power-down means connected in series between said third and fourth true outputs for introducing a voltage differential, said second buffer circuit also producing third and fourth complement address voltages of the same logic state at third and fourth complement outputs, fourth power-down means connected in series between said third and fourth complement outputs for introducing a voltage differential, a decode logic circuit having a first plurality of input devices conected between a voltage supply and output nodes and a second plurality of input devices connected between output nodes and reference potential, the first input devices being conected to said first and third true outputs to receive said first and third true address voltages and connected to said first and third complement outputs to receive said first and third complement address voltages, the second input devices being connected to said second and fourth true outputs to receive said second and fourth true address voltages and connected to said second and fourth complement outputs to receive said second and fourth complement address voltages, and means to apply either an operating voltage or a power-down voltage to said first, second, third and fourth power-down means to define an operating condition in which such voltage differentials are not present or a power-down condition in which such voltage differentials are present.

Claim 7

Address decoding circuitry formed in a semiconductor integrated circuit comprising: a first buffer circuit for receiving a first address bit and producing first and second true address voltages of the same logic state at first and second true outputs, first power-down means. connected in series between said first and second true outputs for introducing a voltage differential, said first buffer circuit also producing first and second complement address voltages of the same logic state at first and second complement outputs, second power-down means connected in series between said first and second complement outputs for introducing a voltage differential, a second buffer circuit for receiving a second address bit and producing third and fourth true address voltages of the same logic state at third and fourth true outputs, third power-down means connected in series between said third and fourth true outputs for introducing a voltage differential, said second buffer circuit also producing third and fourth complement address voltages of the same logic state at third and fourth complement outputs, fourth power-down means connected in series between said third and fourth complement outputs for introducing a voltage differential, a decode logic circuit having a first plurality of input devices conected between a voltage supply and output nodes and a second plurality of input devices connected between output nodes and reference potential, the first input devices being conected to said first and third true outputs to receive said first and third true address voltages and connected to said first and third complement outputs to receive said first and third complement address voltages, the second input devices being connected to said second and fourth true outputs to receive said second and fourth true address voltages and connected to said second and fourth complement outputs to receive said second and fourth complement address voltages, and means to apply either an operating voltage or a power-down voltage to said first, second, third and fourth power-down means to define an operating condition in which such voltage differentials are not present or a power-down condition in which such voltage differentials are present.

Claim 8

Circuitry according to claim 4 wherein said logic circuit is an AND/OR circuit producing a one-of-N decode function, where N is a power of 2.

Claim 9

Circuitry according to claim 4 wherein said input devices are insulated gate field-effect transistors.

Claim 10

A decoder according to claim 1 including means in said logic circuits for establishing a low-power condition in which none of said transistors in said logic inputs of the decoder means is allowed to conduct regardless of the state of said address bits.

Claim 11

A decoder according to claim 1 including logic circuitry in said predecode means for receiving said address bits and complements and establishing a low-power condition in which none of such logic circuitry conducts static current to ground regardless of the state of said address bits.

Claim 12

A transistor circuit having a first input terminal, a second input terminal, and a circuit enable terminal, said circuit comprising: (a) a depletion-mode MOS transistor having a source, a drain, and a gate, the latter gate being connected to said first input terminal; (b) an enhancement-mode MOS transistor having a drain, a source, and a gate, the latter gate being connected to said second input terminal; and (c) an MOS transistor connected between said depletion-mode transistor and said enhancement-mode transistor for providing a power-down function, said power-down function transistor having a threshold voltage of approximately zero volts and also having a drain connected to said source of said depletion-mode MOS transistor, a source connected to said drain of said enhancement-mode transistor, and a gate connected to said circuit enable terminal.

Claim 13

A transistor circuit having a first input terminal, a second input terminal, and a circuit enable terminal, said circuit comprising: (a) a depletion-mode MOS transistor having a source, a drain, and a gate, the latter gate being connected to said first input terminal; (b) an enhancement-mode MOS transistor having a drain, a source, and a gate, the latter gate being connected to said second input terminal; and (c) an MOS transistor connected between said depletion-mode transistor and said enhancement-mode transistor for providing a power-down function, said power-down function transistor having a threshold voltage of approximately zero volts and also having a drain connected to said source of said depletion-mode MOS transistor, a source connected to said drain of said enhancement-mode transistor, and a gate connected to said circuit enable terminal.

Claim 14

The transistor circuit in claim 9, wherein said depletion-mode MOS transistor is a load transistor and said enhancement-mode MOS transistor is a drive transistor.

Claim 15

The transistor circuit in claim 9, wherein a chip select signal is inputted to said circuit enable terminal for enabling or powering-down said circuit.

Claim 16

The transistor circuit in claim 9, wherein an output terminal is connected to said drain of said enhancement-mode MOS transistor.

Claim 17

The transistor circuit in claim 9 further including a power supply having at least two terminals wherein said drain of said depletion-mode MOS transistor is connected to a first terminal of said power supply and said source of said enhancement-mode MOS transistor is connected to a second terminal of said power supply.

Claim 18

The transistor circuit in claim 13 wherein said first terminal of said power supply is at a more positive potential than is said second terminal.

Claim 19

The transistor circuit of claim 9 wherein said first input terminal is an inverted signal input terminal and wherein a first output terminal is connected to said drain of said enhancement-mode transistor.

Claim 20

The transistor circuit in claim 15 further including a second output terminal connected to said drain of said power-down function MOS transistor.