US4143359A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Decoder circuit
Assignee: RCA Corp
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Filing: 1977-12-02
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Granted: 1979-03-06
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Expires: 1997-12-02
Abstract
Abstract Binary coded signals present on N input lines are decoded by means of N differential current switches. Each current switch is connected to a different one of the input lines and produces a group of 2.sup.(N-1) outputs in-phase with its input and a group of 2.sup.(N-1) outputs out-of-phase with its input. 2 N conductors interconnect the outputs of the N switches to produce 2 N decoded outputs, each of which represents a unique combination of the binary signals on the N input lines.
Inventors
- 👤 Howard R. Beelitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 19:50
CPC Classifications
G; G11; G11C; G11C8/00; G11C8/10; H; H03; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03M; H03M7/00; H03M7/001; H03M7/005
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
219 words
A decoder circuit comprising: N input lines, each line adapted to receive an input signal; where N is an integer greater than one; N differential current switches, each switch having: (a) a first input adapted to receive an input signal; (b) a second input adapted to receive a reference potential; (c) 2.sup.(N-1), distinct first outputs at which are produced signals in-phase with the signal applied to said first input; and (d) 2.sup.(N-1) distinct second outputs at which are produced signals out-of-phase with the signal applied to said first input; means connecting each one of said N input lines to a respective one of said first inputs of said N current switches; 2 N conductors; means connecting each one of said 2 N conductors to a distinct combination of one output from each one of said N switches for producing 2 N different combinations of the signals present at said N input lines; and 2 N load means, each load means being connected to a respective one of said 2 N conductors for establishing a first level on a said conductor when all the switch outputs connected to that conductor are in one state and for establishing a second level on said one conductor when all the switch outputs connected to that conductor are not all in said one state.
Claim 2
Dependent Claim
219 words
A decoder circuit comprising: N input lines, each line adapted to receive an input signal; where N is an integer greater than one; N differential current switches, each switch having: (a) a first input adapted to receive an input signal; (b) a second input adapted to receive a reference potential; (c) 2.sup.(N-1), distinct first outputs at which are produced signals in-phase with the signal applied to said first input; and (d) 2.sup.(N-1) distinct second outputs at which are produced signals out-of-phase with the signal applied to said first input; means connecting each one of said N input lines to a respective one of said first inputs of said N current switches; 2 N conductors; means connecting each one of said 2 N conductors to a distinct combination of one output from each one of said N switches for producing 2 N different combinations of the signals present at said N input lines; and 2 N load means, each load means being connected to a respective one of said 2 N conductors for establishing a first level on a said conductor when all the switch outputs connected to that conductor are in one state and for establishing a second level on said one conductor when all the switch outputs connected to that conductor are not all in said one state.
Claim 3
Dependent Claim
56 words
The combination as claimed in claim 1 wherein each one of said N differential current switches comprises first and second transistors, each transistor having a base, an emitter and 2.sup.(N-1) Schottky-barrier collector contacts, whereby each one of said 2.sup.(N-1) collector contacts is isolated by a Schottky diode from the other collector contacts of the same transistor.
Claim 4
Dependent Claim
89 words
The combination as claimed in claim 2 wherein said emitters of said first and second transistors are connected via a relatively constant current source to a point of fixed operating potential; wherein the base of said first transistor is said first input of said current switch, wherein the base of second transistor is said second input of said current switch; wherein said 2.sup.(N-1) collector contacts of said first transistor define said distict first outputs; and wherein said 2.sup.(N-1) collector contacts of said second transistor define said distinct second ouputs.
Claim 5
Dependent Claim
44 words
The combination as claimed in claim 3 wherein each one of said 2 N load means includes a load resistor connected between its associated said conductor and a point of fixed operating potential, and an emitter follower connected at its input to the conductor.
Claim 6
Dependent Claim
30 words
The combination as claimed in claim 4 wherein each one of said load means includes a diode connected across the load resistor for limiting the voltage drop across the resistor.
Claim 7
Dependent Claim
50 words
The combination as claimed in claim 1 wherein each one of said N differential current switches is comprised of first and second transistors, each transistor having a base, an emitter, and 2.sup.(N-1) collectors; each one of said 2.sup.(N-1) collectors being junction isolated from the other collectors of the same transistor.
References Cited (Backward Citations)
US3914620A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-03-05 | 1982-09-04 | 1983-03-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-03-05 | 1986-09-04 | 1987-03-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-03-05 | 1990-09-04 | 1991-03-06 | $7700.00 | Window Closed / Lapsed |