Charge transfer device with pn junction gates

Claim 1

A semiconductor charge transfer device formed in a semiconductor wafer having a pair of principal surfaces, said device including at least one charge transfer train comprising a plurality of cells connected in series, each cell comprising: a first and second semiconductor regions of one conductivity type and of low resistivity formed adjacent to one of said principal surfaces, each of said first and second semiconductor regions having a respective potential associated therewith; a third semiconductor region of high resistivity having said one conductivity type and predetermined width disposed between said first and second semiconductor regions; a fourth semiconductor region of low resistivity and having the opposite conductivity type of said one conductivity type and being disposed between said first and second semiconductor regions thereby forming a diode structure; an insulating layer disposed on said semiconductor regions in each cell; a first electrode formed on said insulating layer and extending from said second region of each of said cells to said fourth region of each ell for controlling the potential of said second and fourth regions; a second electrode formed on said insulating layer and extending from said first region of each of said cells to the fourth region of the next succeeding cell for controlling the potential of said first and fourth regions; controlling means for controllably generating a depletion region and thereby an electric field to effect a drift of charge carriers between said first and second semiconductor regions, said means for controllably generating an electric field including means responsive to a control potential applied thereto for establishing a controllable potential barrier with respect to said charge carriers having the lowest portion of a saddle-shaped region of the potential distribution in the vicinity of said first semiconductor region in accordance with both said control potential and the respective potentials associated with said first and second semiconductor regions, the distance between said first and said saddle-shaped regions being smaller than the distance between said first and said second regions; the length of the potential barrier in the direction of carriers which have passed over this potential barrier to flow quickly by drift motion; and the portion of said insulating layer extending between said third region and said first and second electrodes being thicker than the portion of said insulating layer extending between said first, second, and fourth regions and said electrodes.