Delta modulation encoding/decoding circuitry

Claim 2

In an adaptive delta modulation circuit for generating an analog signal in response to a serial stream of binary logic bits, adaptive coding circuitry comprising: logic means for monitoring a serial stream of binary logic bits and for generating an overload control signal indicative of the onset of slope overload, said logic means generating a logic control signal as said overload control signal, said logic control signal having two binary states, one of said states having a time duration indicative of the extent of slope overload; analog adaptation means responsive to said overload control signal for generating a slope magnitude control signal indicative of a magnitude of slope, said analog adaptive means of generating an adaptation voltage as said slope magnitude control signal which is proportional to the average of the exponential of the average duration of the overload control signal, said analog adaptation means including: circuit means for generating a first voltage proportional to the average of said time duration of said logic control signal; first conversion means for exponentially converting said voltage to an adaptation current; and second conversion means for averaging and converting said adaption current to said adaptation voltage; and integrator means for generating an analog signal formed of line segments each having a slope magnitude characteristic controllable by said slope magnitude control signal and each having a polarity characteristic determined by the logic state of a bit of said serial stream of binary logic bits.

Claim 3

In an adaptive delta modulation circuit for generating an analog signal in response to a serial stream of binary logic bits, adaptive coding circuitry comprising: logic means for monitoring a serial stream of binary logic bits and for generating an overload control signal indicative of the onset of slope overload, said logic means generating a logic control signal as said overload control signal, said logic control signal having two binary states, one of said states having a time duration indicative of the extent of slope overload; analog adaptation means responsive to said overload control signal for generating a slope magnitude control signal indicative of a magnitude of slope, said analog adaptive means of generating an adaptation voltage as said slope magnitude control signal which is proportional to the average of the exponential of the average duration of the overload control signal, said analog adaptation means including: circuit means for generating a first voltage proportional to the average of said time duration of said logic control signal; first conversion means for exponentially converting said voltage to an adaptation current; and second conversion means for averaging and converting said adaption current to said adaptation voltage; and integrator means for generating an analog signal formed of line segments each having a slope magnitude characteristic controllable by said slope magnitude control signal and each having a polarity characteristic determined by the logic state of a bit of said serial stream of binary logic bits.

Claim 4

Adaptive coding circuitry according to claim 1 wherein said circuit means includes voltage averaging means for generating said first voltage; and wherein said first conversion means includes exponential voltage-to-current generator means for generating a first current exponentially related to said first voltage; and wherein said second conversion means includes operational amplifier means for averaging and converting said first current to said adaptation voltage.

Claim 5

Adaptive coding circuitry according to claim 3 wherein said logic means is referenced to a first local ground; and wherein said exponential voltage-to-current generator includes transistor means being referenced to a second local ground isolatable from said first ground.

Claim 6

Adaptive coding circuitry according to claim 3 wherein said operational amplifier means includes capacitive means for controlling the attack and decay rate of said adaptation voltage.

Claim 7

Adaptive coding circuitry according to claim 1 wherein said second conversion means provides a decay rate being substantially independent of the time duration since the last indication of the onset of slope overload.

Claim 8

Adaptive coding circuitry according to claim 6 wherein said logic means generates a logic control signal as said control signal, said logic control signal having a logic HIGH and a logic LOW state; and wherein said decay rate is substantially independent of said logic control signal when said logic control is in its logic LOW state.

Claim 9

In an adaptive delta modulation circuit for generating an analog signal in response to a serial stream of binary logic bits, adaptive coding circuitry comprising: logic means for monitoring a serial stream of binary logic bits and for generating a control signal indicative of the onset of slope overload; analog adaptation means responsive to said overload control signal for generating a slope magnitude control signal indicative of a magnitude of slope; and integrator means for generating an analog signal formed of line segments each having a slope magnitude characteristic controllable by said slope magnitude control signal and each having a polarity characteristic determined by the logic state of a bit of said serial stream of binary logic bits, said integrator means including a sole switch controllable by said serial stream of binary logic bits for shorting to ground a circuit point and responsively changing the polarity characteristic of said analog signal.

Claim 10

In an adaptive delta modulation circuit for generating an analog signal in response to a serial stream of binary logic bits, adaptive coding circuitry comprising: logic means for monitoring a serial stream of binary logic bits and for generating a control signal indicative of the onset of slope overload; analog adaptation means responsive to said overload control signal for generating a slope magnitude control signal indicative of a magnitude of slope; and integrator means for generating an analog signal formed of line segments each having a slope magnitude characteristic controllable by said slope magnitude control signal and each having a polarity characteristic determined by the logic state of a bit of said serial stream of binary logic bits, said integrator means including a sole switch controllable by said serial stream of binary logic bits for shorting to ground a circuit point and responsively changing the polarity characteristic of said analog signal.

Claim 11

Adaptive coding circuitry according to claim 8 wherein said sole switch is operable for switching signal levels at said circuit point within a range of ground to a single-polarity power supply voltage; and wherein said analog signal is referenced to ground and varies both positively and negatively with respect to ground.

Claim 12

Adaptive coding circuitry according to claim 9 wherein the relative magnitude between the positive polarity output slope and the negative polarity output slope is adjustable by a single circuitry component value.

Claim 13

Adaptive coding circuitry according to claim 8 wherein said integrator means includes an operational amplifier for generating said analog signal, the inverting input of said operational amplifier receiving a voltage controllable by said slope magnitude control signal and said noninverting input of said operational amplifier receiving a voltage controllable by said slope magnitude control signal and said switch.