US4042921A
Expired / Lapsed
US
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Digital encoder/decoder
Assignee: Ericsson Australia Pty Ltd
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Filing: 1974-09-17
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Granted: 1977-08-16
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Expires: 1994-09-17
Abstract
Abstract An average peak slope companded delta codec for converting an analog signal to a corresponding digital signal and vice versa includes a comparator which receives an analog signal and a variable reconstruction signal and converts the analog signal into a digital data bit stream. A detector is provided for detecting the presence of preselected sequences of bits in the digital bit stream. An attack/decay signal is generated wherein the signal increases upon the occurrence of the preselected sequence and decreases upon the non-occurrence of the preselected sequence with the ratio of the increase to decrease of the attack/decay signal being in the range of 30:1 to 500:1. A converter means receives the attack/decay signal and generates a compand signal which is substantially an anti-logarithmic function of the attack/decay signal wherein the rate of increase of the compand signal is in the range of 0.75 dB/bit period to 3.0 dB/bit period. The compand signal is accumulated to form the variable reconstruction signal which is coupled to the input of the comparator. A means is provided for inverting the polarity of the compand signal when the reconstruction signal exceeds the analog input signal so that the reconstruction signal changes in value toward the value of the analog signal during each bit period. An average peak slope companded delta codec for converting a digital signal back to an analog signal is also disclosed.
Inventors
- 👤 Peter Leslie Smith
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:48
CPC Classifications
H; H03; H03M; H03M3/00; H03M3/02; H03M3/022; H03M3/024
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
175 words
An average peak slope companded delta codec for converting an analog signal to a digital signal comprising: comparator means receiving said analog signal and a variable construction signal for converting said analog signal to a digital bit stream, detecting means for detecting the presence of at least one preselected sequence of bits in the digital bit stream, means responsive to said detecting means for generating an attack/decay signal which increase upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, converter means receiving said attack/decay signal for providing a compand signal which is substantially an anti-logarithmic function of said attack/decay signal, means for accumulating said compand signal to form said variable reconstruction signal, and polarity inverting means for inverting the polarity of said compand signal when said reconstruction signal exceeds said analog signal, thereby causing said reconstruction signal to change in value toward the value of said analog signal during each bit period, said companding adjusting to the average of the high slope regions of said analog input signal.
Claim 2
Dependent Claim
175 words
An average peak slope companded delta codec for converting an analog signal to a digital signal comprising: comparator means receiving said analog signal and a variable construction signal for converting said analog signal to a digital bit stream, detecting means for detecting the presence of at least one preselected sequence of bits in the digital bit stream, means responsive to said detecting means for generating an attack/decay signal which increase upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, converter means receiving said attack/decay signal for providing a compand signal which is substantially an anti-logarithmic function of said attack/decay signal, means for accumulating said compand signal to form said variable reconstruction signal, and polarity inverting means for inverting the polarity of said compand signal when said reconstruction signal exceeds said analog signal, thereby causing said reconstruction signal to change in value toward the value of said analog signal during each bit period, said companding adjusting to the average of the high slope regions of said analog input signal.
Claim 3
Dependent Claim
216 words
An average peak slope companded delta codec for converting an analogue signal to a digital signal comprising: comparator means receiving said analogue signal and a variable reconstruction signal for converting said analogue signal to a digital bit stream, detecting means for detecting the presence of at least one preselected sequence of bits in the digital bit stream, means responsive to said detecting means for generating an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, converter means receiving said attack/decay signal for providing a compand signal which is substantially an anti-logarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, means for accumulating said compand signal to form said variable reconstruction signal, and polarity inverting means for inverting the polarity of said company signal when said reconstruction signal exceeds said analogue signal, thereby causing said reconstruction signal to change in value toward the value of said analogue signal during each bit period, said compand signal being thereby adjusted to the average of the high slope regions of said analogue input signal.
Claim 4
Dependent Claim
216 words
An average peak slope companded delta codec for converting an analogue signal to a digital signal comprising: comparator means receiving said analogue signal and a variable reconstruction signal for converting said analogue signal to a digital bit stream, detecting means for detecting the presence of at least one preselected sequence of bits in the digital bit stream, means responsive to said detecting means for generating an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, converter means receiving said attack/decay signal for providing a compand signal which is substantially an anti-logarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, means for accumulating said compand signal to form said variable reconstruction signal, and polarity inverting means for inverting the polarity of said company signal when said reconstruction signal exceeds said analogue signal, thereby causing said reconstruction signal to change in value toward the value of said analogue signal during each bit period, said compand signal being thereby adjusted to the average of the high slope regions of said analogue input signal.
Claim 5
Dependent Claim
93 words
The codec of claim 2 wherein said means for generating said attack/decay signal comprises a storage capacitor, and a current pulse generator which generates a current for increasing the voltage across said capacitor upon the detection of said preselected sequence of bits in the digital bit stream and which generates a current for decreasing the voltage across the capacitor in the absence of the detection of said preselected sequence, the ratio of the current for increasing the voltage to the current for decreasing said voltage being in the range of 30:1 to 500:1.
Claim 6
Dependent Claim
35 words
The codec of claim 2 wherein said preselected sequences of bits are four "ones" or four "zeros"and wherein said delta codec is timed by means of a clock signal having a frequency of 64 kHz.
Claim 7
Dependent Claim
220 words
In an average peak slope companded delta codec the method of converting an analogue signal to a digital signal comprising the steps of: comparing said analogue signal with a variable reconstruction signal to thereby convert said analogue signal to a digital bit stream having a value in each of the plurality of bit periods depending on the comparison of said analogue signal with said variable construction signal for said period, detecting the presence of at least one preselected sequence of bits in the digital bit stream, generating in response to the detected preselected sequence an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, generating a compand signal in response to said attack/decay signal which is substantially an antilogarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, accumulating said compand signal to form said variable reconstruction signal, and selectively inverting the polarity of said compand signal when said reconstruction signal exceeds said analogue signal thereby causing said reconstruction signal to change in value toward the value of said analogue signal during each bit period.
Claim 8
Dependent Claim
220 words
In an average peak slope companded delta codec the method of converting an analogue signal to a digital signal comprising the steps of: comparing said analogue signal with a variable reconstruction signal to thereby convert said analogue signal to a digital bit stream having a value in each of the plurality of bit periods depending on the comparison of said analogue signal with said variable construction signal for said period, detecting the presence of at least one preselected sequence of bits in the digital bit stream, generating in response to the detected preselected sequence an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, generating a compand signal in response to said attack/decay signal which is substantially an antilogarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, accumulating said compand signal to form said variable reconstruction signal, and selectively inverting the polarity of said compand signal when said reconstruction signal exceeds said analogue signal thereby causing said reconstruction signal to change in value toward the value of said analogue signal during each bit period.
Claim 9
Dependent Claim
76 words
The method of claim 5 wherein said attack/decay signal generating step comprises the steps of generating a current for increasing the voltage across a storage capacitor upon the detection of said preselected sequence and generating a current to decrease the voltage across said storage capacitor in the absence of said preselected sequence wherein the ratio of current to increase the voltage to the current for decreasing the voltage being in the range of 30:1 to 500:1.
Claim 10
Dependent Claim
33 words
The method of claim 6 wherein said preselected sequence includes the sequence of four "ones" or four "zeros" and further comprising the step of clocking said codec with a frequency of 64 kHz.
Claim 11
Dependent Claim
187 words
An average peak slope companded delta codec for converting a digital bit stream to an analogue signal comprising detecting means for detecting the presence of at least one preselected sequence of bits in the digital bit stream, means responsive to said detecting means for generating an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, converter means receiving said attack/decay signal for providing a compand signal which is substantially an anti-logarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, means for accumulating said compand signal to form a reconstruction signal, means for inverting the polarity of said compand signal upon the change of value of an input bit in said digital bit stream to thereby change the value of said reconstruction signal, and means for filtering said reconstruction signal to thereby provide an analogue signal corresponding to said digital bit stream.
Claim 12
Dependent Claim
187 words
An average peak slope companded delta codec for converting a digital bit stream to an analogue signal comprising detecting means for detecting the presence of at least one preselected sequence of bits in the digital bit stream, means responsive to said detecting means for generating an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, converter means receiving said attack/decay signal for providing a compand signal which is substantially an anti-logarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, means for accumulating said compand signal to form a reconstruction signal, means for inverting the polarity of said compand signal upon the change of value of an input bit in said digital bit stream to thereby change the value of said reconstruction signal, and means for filtering said reconstruction signal to thereby provide an analogue signal corresponding to said digital bit stream.
Claim 13
Dependent Claim
87 words
The codec of claim 8 wherein said means for generating said attack/decay signal comprises a storage capacitor, and a current pulse generator for generating a current for increasing the voltage on said capacitor upon the detection of said preselected sequences and for generating a current for decreasing the voltage on said capacitor in the absence of said preselected sequence, the ratio of the current for increasing the voltage across said capacitor to the current for decreasing the voltage thereacross being in the range of 30:1 to 500:1.
Claim 14
Dependent Claim
30 words
The codec of claim 8 wherein the preselected sequence of bits includes four "ones" or four "zeros" and wherein said codec is operated from a clerk frequency of 64 kHz.
Claim 15
Dependent Claim
190 words
In an average peak slope companded delta codec a method of converting a digital bit stream to an analogue signal comprising the steps of: detecting the presence of at least one preselected sequence of bits in said digital bit stream, generating in response to the detected preselected sequence an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, generating a compand signal in response to said attack/decay signal which is substantially an antilogarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, accumulating said compand signal to form a variable reconstruction signal, selectively reversing the polarity of said compand signal when an input bit of said digital bit stream changes its state to thereby vary the amplitude of said reconstruction signal, and means for filtering said reconstruction signal to provide an analogue signal which varies in accordance with the information in said digital bit stream.
Claim 16
Dependent Claim
190 words
In an average peak slope companded delta codec a method of converting a digital bit stream to an analogue signal comprising the steps of: detecting the presence of at least one preselected sequence of bits in said digital bit stream, generating in response to the detected preselected sequence an attack/decay signal which increases upon the occurrence of said preselected sequence and decreases upon the non-occurrence of said preselected sequence, the ratio of increase to decrease of said attack/decay signal being in the range of 30:1 to 500:1, generating a compand signal in response to said attack/decay signal which is substantially an antilogarithmic function of said attack/decay signal, the rate of increase of said compand signal being in the range of 0.75 dB/bit period to 3.0 dB/bit period, accumulating said compand signal to form a variable reconstruction signal, selectively reversing the polarity of said compand signal when an input bit of said digital bit stream changes its state to thereby vary the amplitude of said reconstruction signal, and means for filtering said reconstruction signal to provide an analogue signal which varies in accordance with the information in said digital bit stream.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-15 | 1981-02-14 | 1981-08-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-15 | 1985-02-14 | 1985-08-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-15 | 1989-02-14 | 1989-08-16 | $7700.00 | Window Closed / Lapsed |