← Back to Patent Explorer
US3855555A Expired / Lapsed US ⏱️ 0.0 years remaining

Delta modulator having low-level random noise characteristic

Assignee: Knowles Electronics LLC
•
Filing: 1972-08-25
•
Granted: 1974-12-17
•
Expires: 1992-08-25
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A delta modulator for analog-digital conversion, comprising a high gain comparator amplifier connected to the input of a clockcontrolled sampling flip-flop circuit; an audio signal is applied to the input of the comparator and a principal integrating circuit of short time constant develops a replica of the audio signal from the output of the flip-flop, and applies the replica to the comparator in bucking relation to the original audio signal. A self-bias variable D.C. reference signal is derived from the flip-flop output and is applied to the other comparator input; the bias circuit also transmits a negative feedback A.C. signal of limited amplitude, asymmetrical with respect to polarity, introducing a limited amplitude broad-band random noise into the demodulated output signal for idling (zero or very small input) conditions.

Inventors

  • 👤 M Burkhard
  • 👤 R Peters

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-23 15:59
CPC Classifications
G; G01; G01H; G01H7/00; H; H03; H03M; H03M3/00; H03M3/02

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 279 words
A delta modulator, suitable for audio signal processing, which provides a subjectively tolerable low-level random idling noise in the demodulated output of the modulator, comprising: high-gain comparator amplifier means having two inputs and an output; input means for applying an initial analog signal to one input of the comparator amplifier means; a sampling gate comprising a flip-flop circuit having a main input, a sampling input, and first and second outputs, one of the gate outputs comprising the modulator output, the main input of the sampling gate being connected to the output of the comparator amplifier means; clock means for applying a high-frequency clock signal to the sampling input of the gate to control actuation of the gate between two alternate operating conditions and generate two output pulse signals of inverse polarity at the gate outputs; a principal integrating negative feedback circuit, having a short time constant, connected from one output of the sampling gate to one input of the comparator amplifier means, for integrating one pulse signal from the gate to develop a replica analog signal and for applying that replica signal to the comparator amplifier means in bucking relation to the initial analog signal; and a self-bias feedback circuit, comprising an integrating circuit having a long time constant, connected from one output of the sampling gate to one input of the comparator amplifier means, for applying a self-bias reference to the comparator amplifier means, the self-bias feedback circuit also transmitting a negative feedback A.C. signal of limited amplitude to introduce a limited broad-band noise content into the output signal of the modulator; one of the feedback circuits being connected to the other input of the comparator amplifier means.
Claim 2
Dependent Claim 279 words
A delta modulator, suitable for audio signal processing, which provides a subjectively tolerable low-level random idling noise in the demodulated output of the modulator, comprising: high-gain comparator amplifier means having two inputs and an output; input means for applying an initial analog signal to one input of the comparator amplifier means; a sampling gate comprising a flip-flop circuit having a main input, a sampling input, and first and second outputs, one of the gate outputs comprising the modulator output, the main input of the sampling gate being connected to the output of the comparator amplifier means; clock means for applying a high-frequency clock signal to the sampling input of the gate to control actuation of the gate between two alternate operating conditions and generate two output pulse signals of inverse polarity at the gate outputs; a principal integrating negative feedback circuit, having a short time constant, connected from one output of the sampling gate to one input of the comparator amplifier means, for integrating one pulse signal from the gate to develop a replica analog signal and for applying that replica signal to the comparator amplifier means in bucking relation to the initial analog signal; and a self-bias feedback circuit, comprising an integrating circuit having a long time constant, connected from one output of the sampling gate to one input of the comparator amplifier means, for applying a self-bias reference to the comparator amplifier means, the self-bias feedback circuit also transmitting a negative feedback A.C. signal of limited amplitude to introduce a limited broad-band noise content into the output signal of the modulator; one of the feedback circuits being connected to the other input of the comparator amplifier means.
Claim 3
Dependent Claim 27 words
A delta modulator, according to claim 1, in which the self-bias feedback circuit includes a non-linear impedance affording a random idling characteristic in operation of the modulator.
Claim 4
Dependent Claim 41 words
A delta modulator, according to claim 2, in which the principal feedback circuit is connected back to the input of the comparator amplifier means and the self-bias feedback circuit is connected back to the other input of the comparator amplifier means.
Claim 5
Dependent Claim 41 words
A delta modulator, according to claim 2, in which the self bias feedback circuit includes two linear impedances connected in parallel and in which the non-linear impedance comprises a unidirectionally conductive device connected in series with one of the linear impedances.
Claim 6
Dependent Claim 22 words
A delta modulator, according to claim 4, in which the unidirectionally conductive device is a diode and the linear impedances are resistances.
Claim 7
Dependent Claim 40 words
A delta modulator, according to claim 1, in which the self bias feedback circuit comprises a series resistance and a shunt capacitance, and a very small resistance, as compared with the series resistance, connected in series with the shunt capacitance.

References Cited (Backward Citations)

US3453562A Cited
US3643180A Cited
US3646442A Cited
US3703688A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1977-12-16 1978-06-17 1978-12-17 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1981-12-16 1982-06-17 1982-12-17 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1985-12-16 1986-06-17 1986-12-17 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag