Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
214 words
For use with a wire-OR bus circuit including a bus wire (10), and a plurality of bus-coupled circuits, connected to said bus wire at different points along its length, a bus-coupled circuit comprising: a first input (38) for receiving a data signal to be transmitted on said bus wire, said data signal including at least two voltage levels, said signal making transitions between said levels at prescribed times; a first output (39) coupled to said bus wire (10) at a first point along its length; signal amplifier means (34), coupling said first input (38) and said first output (39), for amplifying said data signal prior to presentation to said bus wire; and, a bus precharge circuit (16); said bus precharge circuit having a second input (36) for receiving a control signal (20); said bus precharge circuit having a second output (40), connected to said bus wire (10) at a second point along its length, for presenting electrical precharge pulses to said bus wire in response to said control signal (20); said electrical precharge pulses being applied to said bus wire in synchronism with said data signal in such a way that said electrical precharge pulse is applied to said bus wire (10) at approximately the instant of time of an expected data signal transition.
Claim 2
Dependent Claim
214 words
For use with a wire-OR bus circuit including a bus wire (10), and a plurality of bus-coupled circuits, connected to said bus wire at different points along its length, a bus-coupled circuit comprising: a first input (38) for receiving a data signal to be transmitted on said bus wire, said data signal including at least two voltage levels, said signal making transitions between said levels at prescribed times; a first output (39) coupled to said bus wire (10) at a first point along its length; signal amplifier means (34), coupling said first input (38) and said first output (39), for amplifying said data signal prior to presentation to said bus wire; and, a bus precharge circuit (16); said bus precharge circuit having a second input (36) for receiving a control signal (20); said bus precharge circuit having a second output (40), connected to said bus wire (10) at a second point along its length, for presenting electrical precharge pulses to said bus wire in response to said control signal (20); said electrical precharge pulses being applied to said bus wire in synchronism with said data signal in such a way that said electrical precharge pulse is applied to said bus wire (10) at approximately the instant of time of an expected data signal transition.
Claim 3
Dependent Claim
27 words
The bus circuit defined in claim 1, wherein said second output (40) is connected to said bus wire at a common point with said first output (39).
Claim 4
Dependent Claim
27 words
The bus circuit in accordance with claim 1, wherein said said signal amplifier means (22) includes a first amplifying transistor (34) connected to said first output (39).
Claim 5
Dependent Claim
26 words
The bus circuit in accordance with claim 3, wherein said bus precharge circuit (16) includes a second amplifying transistor (32) connected to said second output (40).
Claim 6
Dependent Claim
78 words
The bus circuit in accordance with claim 4, wherein said first and second transistors (32, 34) each have a current control terminal for applying a current control signal to the transistor, and two current flow terminals for passing current through the transistor; whereby each one of said first transistors is associated with one of said second transistors such that a current flow terminals of said first transistor is connected to a current flow terminal of said second transistor.
Claim 7
Dependent Claim
49 words
The bus circuit in accordance with claim 5, wherein said first transistor (34) is connected in series with said second transistor (32) and wherein said first and said second outputs (39, 40) are taken from the series interconnection between the current flow terminals of said first and second transistors.
Claim 8
Dependent Claim
29 words
The bus circuit in accordance with claim 1, further comprising means (R1, R2; R3, R4) for biasing each end of said bus wire (10) at a prescribed voltage level.
Claim 9
Dependent Claim
160 words
The bus circuit defined in claim 1 further including a pulse-generating means for producing said control signal (20), comprising: a differentiating circuit (50) responsive to a transition in a bus clock signal (59); a one shot (52); said one-shot (52) being capable of producing a first pulse of arbitrary width; said differentiating circuit (50) producing a second pulse at the instant of said transition in said bus clock signal (59) and supplying said second pulse as a trigger input to said one shot (52); an AND-gate (54); a time-delay circuit (56); said first pulse being supplied to both said AND-gate (54) and said time-delay circuit (56); said second pulse being delayed at the output of said time-delay circuit by a time delay (delta T) to thereby produce a third pulse; said first and third pulses being passed to said AND-gate (54) which produces a negative output pulse of width delta T in response to said input first and third pulses.
Claim 10
Dependent Claim
61 words
The bus circuit defined in claim 4, wherein there is a substantial difference in size between the said first amplifying transistor (34) and said second amplifying transistor (32), first transistor preferably being approximately 25 times larger in physical size than said second transistor so that said first transistor may deliver about 40 times the amount of current of said second transistor.