FET read only memory cell with word line augmented precharging of the bit lines

Claim 2

In an FET read only memory array including a plurality of FET array devices accessed by a plurality of word lines and outputting stored signals on a plurality of bit lines, the improvement comprising: a first one of said FET array devices having its source/drain path selectively connected between a first one of said bit lines and a first one of said word lines and its gate connected to said first word line, for selectively representing a first stored information state; precharge means connected to said first bit line, for providing electrical charge to said first bit line; said first word line providing a supplementary charge to said first bit line through said source/drain path of said first FET device in said first information state; said first FET array device having its source/drain path selectively alternately connected between said first one of said bit lines and a reference potential, for selectively representing a second stored information state.

Claim 3

The apparatus of claim 1, which further comprises: a reference conductor line disposed proximate to said first FET device in said array, for connection to said reference potential; a conductor tab connected to the side of said source/drain path of said first FET device opposite from said first bit line and selectively connected to said word line to selectively store said first information state; said conductor tab selectively alternately connected to said reference potential line to selectively store said second information state.

Claim 4

In an FET read only memory array including a plurality of FET array devices, each said array device being connected to one of a plurality of bit lines which are precharged to a first potential state during a first interval, each said array device being connected to one of a plurality of word lines which applies substantially said first potential during a second interval following said first interval, rendering the respective array device conductive, the improvement comprising: a first one of said FET array devices having its source connected to a first one of said bit lines, having its gate connected to a first one of said word lines, and having its drain selectively connected to said first word line, representing a first binary state stored by said first array device, said first potential on said first word line serving to augment said precharged state of said first bit line during said second interval so that said first bit line remains at substantially said first potential during a sensing interval following said second interval; a second one of said FET array devices having its drain connected to a second one of said bit lines, having its gate connected to a second one of said word lines, and having its source selectively connected to a second potential different from said first potential, representing a second binary state stored by said second array device, said second array device discharging said second bit line during said second interval so that said second bit line assumes substantially said second potential during said sensing interval; whereby the effects of charge leaking from said bit lines can be minimized.

Claim 5

In an FET read only memory array including a plurality of FET array devices, each said array device being connected to one of a plurality of bit lines which are precharged to a first potential state during a first interval, each said array device being connected to one of a plurality of word lines which applies substantially said first potential during a second interval following said first interval, rendering the respective array device conductive, the improvement comprising: a first one of said FET array devices having its source connected to a first one of said bit lines, having its gate connected to a first one of said word lines, and having its drain selectively connected to said first word line, representing a first binary state stored by said first array device, said first potential on said first word line serving to augment said precharged state of said first bit line during said second interval so that said first bit line remains at substantially said first potential during a sensing interval following said second interval; a second one of said FET array devices having its drain connected to a second one of said bit lines, having its gate connected to a second one of said word lines, and having its source selectively connected to a second potential different from said first potential, representing a second binary state stored by said second array device, said second array device discharging said second bit line during said second interval so that said second bit line assumes substantially said second potential during said sensing interval; whereby the effects of charge leaking from said bit lines can be minimized.

Claim 6

The apparatus of claim 3, which further comprises: precharge means connected to said first bit line, for providing electrical charge to said first bit line; said first word line providing a supplementary charge to said first bit line through the source/drain path of said first FET device when a first tab is connected to said first word line; said second word line providing a supplementary charge to said first bit line through said source/drain path of said second FET device when a second tab is connected to said second word line.

Claim 7

The apparatus of claim 4, wherein said precharge means further comprising: a first zero threshold voltage FET device connected between said first bit line and a second reference potential.

Claim 8

The apparatus of claim 5, which further comprises: a second zero threshold voltage FET device connected between said first bit line and a sensing means, for outputting the voltage corresponding to the stored information state of said first or second FET devices in said array.

Claim 9

In an FET read-only memory array including a plurality of FET array devices accessed by a plurality of word lines and outputting stored signals on a plurality of bit lines, the improvement comprising: a first one of said FET array devices having a source/drain path selectively connected between a first one of said bit lines and a first one of said work lines and its gate connected to said first word line, for selectively representing a first stored information state; said first FET array device having its source/drain path selectively alternately connected between said first one of said bit lines and a reference potential, for selectively representing a second stored information state; a first reference conductor line disposed proximate to said first FET device in said array, for connection to said reference potential; a first conductor tab connected to the side of said source/drain path of said first FET device opposite from said first bit line and selectively connected to said first word line to selectively store said first information state; said first conductor tab selectively alternately connected to said first reference potential line to selectively store said second information state; a second one of said FET array devices having its source/drain path selectively connected between said first one of said bit lines and a second one of said word lines and its gate connected to said second work line, for selectively representing said first stored information state therein; said second FET array device having its source/drain path selectively alternately connected between said first one of said bit lines and said reference potential, for selectively representing said second stored information state therein; a second reference conductor line disposed proximate to said second FET device in said array, for connection to said reference potential; a second conductor tab connected to the side of said source/drain path of said second FET device opposite from said first bit line and selectively connected to said second word line to selectively store said first information state therein; said second conductor tab selectively alternately connected to said second reference potential line to selectively store said second information state in said second FET device.

Claim 10

In an FET read-only memory array including a plurality of FET array devices accessed by a plurality of word lines and outputting stored signals on a plurality of bit lines, the improvement comprising: a first one of said FET array devices having a source/drain path selectively connected between a first one of said bit lines and a first one of said work lines and its gate connected to said first word line, for selectively representing a first stored information state; said first FET array device having its source/drain path selectively alternately connected between said first one of said bit lines and a reference potential, for selectively representing a second stored information state; a first reference conductor line disposed proximate to said first FET device in said array, for connection to said reference potential; a first conductor tab connected to the side of said source/drain path of said first FET device opposite from said first bit line and selectively connected to said first word line to selectively store said first information state; said first conductor tab selectively alternately connected to said first reference potential line to selectively store said second information state; a second one of said FET array devices having its source/drain path selectively connected between said first one of said bit lines and a second one of said word lines and its gate connected to said second work line, for selectively representing said first stored information state therein; said second FET array device having its source/drain path selectively alternately connected between said first one of said bit lines and said reference potential, for selectively representing said second stored information state therein; a second reference conductor line disposed proximate to said second FET device in said array, for connection to said reference potential; a second conductor tab connected to the side of said source/drain path of said second FET device opposite from said first bit line and selectively connected to said second word line to selectively store said first information state therein; said second conductor tab selectively alternately connected to said second reference potential line to selectively store said second information state in said second FET device.

Claim 11

The apparatus of claim 7, which further comprises: a first region of a first conductivity type in a semiconductor substrate of a second conductivity type, for serving as the drain of said first FET device; a second region of said first conductivity type in said substrate, spaced from said first region to define a first channel region therebetween, for serving as the source of said first FET device and the drain of said second FET device; a third region of said first conductivity type in said substrate, spaced from said second region to define a second channel region therebetween, for serving as the source of said second FET device; a first gate electrode located above said first channel region and connected to said first word line, for forming said first FET device; a second gate electrode located above said second channel region and connected to said second word line, for forming said second FET device; said first bit line connected to said second region of said first conductivity type; said first tab connected to said first region of said first conductivity type, for selectively connecting to either said first word line or said first reference potential line; said second tab connected to said third region of said first conductivity type, for selectively connecting to either said second word line or said second reference potential line.