Digital signal multiplex device

Claim 2

A digital signal multiplex device comprising: a multiplex portion comprising first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which every n th time slot in the pulse frame of the intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for the main information to be transmitted and for a first stuffable bit, second channel means for converting four 139.264 Mbit/s signals into the first synchronous intermediate time division multiplex signals in which every n th time slot in the pulse frame of the intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for the four main information to be transmitted interlaced bit-by-bit and for respectively one first and m second stuffable bits including means for providing for four 139.264 Mbit/s signals a superframe of four pulse frames in which a stuffing information and a channel number of a 139.264 Mbit/s signal are inserted in each pulse frame as auxiliary signals, and a multiplexer connected to said first and second channel means for interlacing the intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; and a demultiplex portion for demultiplexing the first time division multiplex signal of a higher order into second intermediate time division multiplex signals, including third channel means for converting second intermediate time division multiplex signals into plesiochronic 564.992 Mbit/s signals by destuffing and blanking of auxiliary signals, and fourth channel means for converting second intermediate time division multiplex signals into plesiochronic 139.264 Mbit/s signals by destuffing and blanking of auxiliary signals.

Claim 3

The digital multiplex device of claim 1, wherein: each of said first and second channel means comprises means for providing a bit repetition frequency of 600.832 Mbit/s and a pulse frame having 544 time slots, where n=17 and m=1 are selected for the intermediate time division multiplex signals.

Claim 4

The digital signal multiplex device of claim 2, wherein: pulse frame dividing means divides the pulse frame into first, second, third and fourth sets each comprising 136 time slots in which in the sequence of the 17 th time slots of the first set the first five time slots are provided for a frame recognition word, the sixth and seventh time slots are cyclically provided for the channel number and the eighth time slot is provided for a first parity bit regarding the main information bits in the second and third sets of the preceding pulse frame, in which in the sequence of the 17 th time slots of the second and fourth sets, service information is provided, and in which in the sequence of the 17 th time slots of the third set the first five time slots are provided for a stuffing information, the sixth and seventh time slots are provided for an order number of the intermediate time division multiplex signal to be formed and the eighth time slot is provided for a second parity bit regarding the main information bits in the fourth set of the preceding pulse frame and in the first set of the current pulse frame.

Claim 5

The digital signal multiplex device of claim 2, wherein: said first channel means comprises means operable with respect to a 564.992 Mbit/s signal to provide that the 128 th time slot in the third set is for the first stuffable bit to be stuffed dependent on the stuffing information or to transmit main information.

Claim 6

The digital signal multiplex device of claim 2, wherein: said second channel means comprises, for the four 139.264 Mbit/s signals, means operable to provide the 128 th through 131 st time slots of the third set for first stuffable bits, to provide the 128 th through 131 st time slots in the first set for second stuffable bits, and to provide that the first stuffable bit in those 139.264 Mbit/s signals whose channel number is in the respective pulse frame is stuffed dependent on the stuffing information in the pulse frame or is occupied with main information, and to provide that all other first and second stuffable bits are stuffed in a fixed manner.

Claim 7

The digital signal multiplex device of claim 1, wherein: said first and second channel means include means for providing a bit repetition frequency of 621.776 Mbit/s and a pulse frame comprising 1056 time slots, where n=11 and m=3 and m=2 in alternation are selected for the intermediate time division multiplex signals.

Claim 8

The digital signal multiplex device of claim 1, and further comprising: means for providing that the pulse frames of the first intermediate time division multiplex signals are synchronous.

Claim 9

A digital signal multiplex device, comprising: a multiplex portion including first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which ever nth time slot and the pulse frame of the first intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information to be transmitted and a first stuffable bit, second channel means for converting four 139.264 mbit/s signals into second synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the second intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information from the four 139.264 Mbit/s signals, transmitted interlaced bit-by-bit, and one first and m second stuffable bits, means for providing the four 139.264 Mbit/s signals with a superframe of four pulse flames in each of which a stuffable information and a channel number of a 139.264 Mbit/s signal are inserted as auxiliary signals, and a multiplexer connected to said first and second channel means for interlacing the first and second intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; bit repetition means for each of said first and second channel means for providing a bit repetition frequency of 621.776 Mbit/s and a pulse frame comprising 1,056 time slots, where n equals 11 and m equals 3 and m equals 2 in alternation; and a demultiplex portion for demultiplexing the first time division multiplex signal of a higher order into third intermediate time division multiplex signals including third channel means for converting the third intermediate time division multiplex signals into plesiochronic 564.992 Mbit/s signals by destuffing and blanking of the auxiliary signals, and fourth channel means for converting the third intermediate time division multiplex signals into plesiochronic 139.264 Mbit/s signals by destuffing and blanking of auxiliary signals.

Claim 10

A digital signal multiplex device, comprising: a multiplex portion including first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which ever nth time slot and the pulse frame of the first intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information to be transmitted and a first stuffable bit, second channel means for converting four 139.264 mbit/s signals into second synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the second intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information from the four 139.264 Mbit/s signals, transmitted interlaced bit-by-bit, and one first and m second stuffable bits, means for providing the four 139.264 Mbit/s signals with a superframe of four pulse flames in each of which a stuffable information and a channel number of a 139.264 Mbit/s signal are inserted as auxiliary signals, and a multiplexer connected to said first and second channel means for interlacing the first and second intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; bit repetition means for each of said first and second channel means for providing a bit repetition frequency of 621.776 Mbit/s and a pulse frame comprising 1,056 time slots, where n equals 11 and m equals 3 and m equals 2 in alternation; and a demultiplex portion for demultiplexing the first time division multiplex signal of a higher order into third intermediate time division multiplex signals including third channel means for converting the third intermediate time division multiplex signals into plesiochronic 564.992 Mbit/s signals by destuffing and blanking of the auxiliary signals, and fourth channel means for converting the third intermediate time division multiplex signals into plesiochronic 139.264 Mbit/s signals by destuffing and blanking of auxiliary signals.

Claim 11

The digital signal multiplex device of claim 8, wherein: said second channel means comprises means operable with respect to the four 139.264 Mbit/s signals that the 256 th through 259 th time slots of the fourth set are provided for a first stuffable bit, that the 256 th through 259 th slot time in every second pulse frame in the first set are provided for second stuffable bits, that in the second and third sets, the respectively 256 th through 259 th time slots are provided for second stuffable bits, that the first stuffable bit in those 139.264 Mbit/s signals whose channel number resides in the respective pulse frame is stuffed dependent on the stuffing information in that pulse frame or is occupied with main information, and that all other first and second stuffable bits are stuffed in a fixed manner.

Claim 12

The digital signal multiplex device of claim 8, wherein: pulse frame division means is provided for dividing the pulse frame into first, second, third and fourth sets each comprising 264 time slots, in which in the sequence of the eleventh time slots, eleven time slots are provided for a frame recognition word, for the channel number, for an order number of the intermediate time division multiplex signal to be formed, and for parity bits regarding the useful information bits of the preceding pulse frame, in which in the sequence of the eleventh time slots, 80 time slots are provided for service information, and in which in the sequence of the eleventh time slots, five time slots are provided for a stuffing information.

Claim 13

The digital signal multiplex device of claim 8, wherein: said first channel means comprises means operable with respect to a 564.992 Mbit/s signal to selectively provide that the 256 th time slot of the fourth set is provided for the first stuffable bit to be stuffed dependent on the stuffing information or to transmit main information.

Claim 14

A digital signal multiplex device, comprising: a multiplex portion including first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the first intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information to be transmitted and a first stuffable bit, second channel means for converting four 139.264 Mbit/s signals into second synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the second intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information from the 139.264 Mbit/s signals, transmitted interlaced bit-by-bit, and one first and m second stuffable bits, means for providing the four 139.264 Mbit/s signals with a superframe of fourth pulse frames in each of which stuffing information and a channel number of a 139.264 Mbit/s signal are inserted as auxiliary signals, and a multiplexer connected to said first and second channel means for interlacing the first and second intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; a demultiplex portion for demultiplexing the first time division multiplex signal of a higher order into third intermediate time division multiplex signals, including third channel means for converting the third channel time division multiplex signals into plesiochronic 564.992 Mbit/s signals by destuffing and blanking of the auxiliary signals, and fourth channel means for converting the third intermediate time division multiplex signals into plesiochronic 139.264 Mbit/s signals by destuffing and blanking of the auxiliary signals; bit repetition frequency means for each of said first and second channels for providing a bit repetition frequency of 600.832 Mbit/s and a pulse frame having 544 time slots, where n equals 17 and m equals 1; and pulse frame division means for dividing the pulse frame into first, second, third, and fourth sets, each st comprising 136 time slots in which in the sequence of the 17th time slots of the first set, the first five time slots are provided for a frame recognition word, the sixth and seventh time slots are cyclicly provided for the channel number and the eighth time slot is provided for a first parity bit regarding the main information bits in the second and third sets of the preceding pulse frame, in which in the sequence of the 17th time slots of the second and fourth sets, service information is provided, and in which iu the sequence of the 17th time slots of the third set, the first five time slots are provided for stuffing information, the sixth and seventh time slots are provided for an order number of the intermediate time division multiplex signal to be formed and the eighth time slot is provided for a second parity bit regarding the main information bits in the fourth set of the preceding pulse frame and in the first set of the current pulse frame.

Claim 15

A digital signal multiplex device, comprising: a multiplex portion including first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the first intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information to be transmitted and a first stuffable bit, second channel means for converting four 139.264 Mbit/s signals into second synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the second intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information from the 139.264 Mbit/s signals, transmitted interlaced bit-by-bit, and one first and m second stuffable bits, means for providing the four 139.264 Mbit/s signals with a superframe of fourth pulse frames in each of which stuffing information and a channel number of a 139.264 Mbit/s signal are inserted as auxiliary signals, and a multiplexer connected to said first and second channel means for interlacing the first and second intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; a demultiplex portion for demultiplexing the first time division multiplex signal of a higher order into third intermediate time division multiplex signals, including third channel means for converting the third channel time division multiplex signals into plesiochronic 564.992 Mbit/s signals by destuffing and blanking of the auxiliary signals, and fourth channel means for converting the third intermediate time division multiplex signals into plesiochronic 139.264 Mbit/s signals by destuffing and blanking of the auxiliary signals; bit repetition frequency means for each of said first and second channels for providing a bit repetition frequency of 600.832 Mbit/s and a pulse frame having 544 time slots, where n equals 17 and m equals 1; and pulse frame division means for dividing the pulse frame into first, second, third, and fourth sets, each st comprising 136 time slots in which in the sequence of the 17th time slots of the first set, the first five time slots are provided for a frame recognition word, the sixth and seventh time slots are cyclicly provided for the channel number and the eighth time slot is provided for a first parity bit regarding the main information bits in the second and third sets of the preceding pulse frame, in which in the sequence of the 17th time slots of the second and fourth sets, service information is provided, and in which iu the sequence of the 17th time slots of the third set, the first five time slots are provided for stuffing information, the sixth and seventh time slots are provided for an order number of the intermediate time division multiplex signal to be formed and the eighth time slot is provided for a second parity bit regarding the main information bits in the fourth set of the preceding pulse frame and in the first set of the current pulse frame.

Claim 16

A digital signal multiplex device, comprising: a multiplex portion including first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the first intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information to be transmitted and a first stuffable bit, second channel means for converting four 139.264 Mbit/s signals into second synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the second intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information from the four 139.264 Mbit/s signals, transmitted interlaced bit-by-bit, and one first and m second stuffable bits, means for providing the four 139.264 Mbit/s signals with a superframe of four pulse frames in which stuffing information and a channel number of a 139.264 Mbit/s signal are inserted as auxiliary signals, and a multiplex connected to said first and second channel means for interlacing the first and second intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; bit repetition means for each of said first and second channels for providing a bit repetition frequency of 600.832 Mbit/s and a pulse frame having 544 time slots, where n equals 17 and m equals 1; pulse frame division means for dividing the pulse frame into first, second, third, and fourth sets; and means operable and associated with said second channel means for providing for the four 139.264 Mbit/s signals, the 128th through 131st time slots of the third set for first stuffable bits, the 128th through 131st time slots in the first set for second stuffable bits, that the first stuffable bit in does 139.264 Mbit/s signals whose channel number is in the respective pulse frame is stuffed dependent on the stuffing information in the pulse frame or is occupied with main information, and that all other first and second stuffable bits are stuffed in a fixed manner.

Claim 17

A digital signal multiplex device, comprising: a multiplex portion including first channel means for converting 564.992 Mbit/s signals into first synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the first intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information to be transmitted and a first stuffable bit, second channel means for converting four 139.264 Mbit/s signals into second synchronous intermediate time division multiplex signals in which every nth time slot in the pulse frame of the second intermediate time division multiplex signals is provided for auxiliary signals and the remaining time slots are provided for main information from the four 139.264 Mbit/s signals, transmitted interlaced bit-by-bit, and one first and m second stuffable bits, means for providing the four 139.264 Mbit/s signals with a superframe of four pulse frames in which stuffing information and a channel number of a 139.264 Mbit/s signal are inserted as auxiliary signals, and a multiplex connected to said first and second channel means for interlacing the first and second intermediate time division multiplex signals bit-by-bit to form a first time division multiplex signal of a higher order; bit repetition means for each of said first and second channels for providing a bit repetition frequency of 600.832 Mbit/s and a pulse frame having 544 time slots, where n equals 17 and m equals 1; pulse frame division means for dividing the pulse frame into first, second, third, and fourth sets; and means operable and associated with said second channel means for providing for the four 139.264 Mbit/s signals, the 128th through 131st time slots of the third set for first stuffable bits, the 128th through 131st time slots in the first set for second stuffable bits, that the first stuffable bit in does 139.264 Mbit/s signals whose channel number is in the respective pulse frame is stuffed dependent on the stuffing information in the pulse frame or is occupied with main information, and that all other first and second stuffable bits are stuffed in a fixed manner.