US3987248A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Digital multiplexing system
Assignee: Societe Anonyme de Telecommunications SAT
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Filing: 1974-11-25
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Granted: 1976-10-19
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Expires: 1994-11-25
Abstract
Abstract In the field of digital data multiplexing systems, the master rates assigned to the different channels are defined by the national Telecommunications Authorities. It may and actually does happen that the master rates differ in different countries. A direct bit per bit multiplexing system from a first low master rate to a second high master rate is proposed which allows demultiplexing the high-rate digital signal into intermediate-rate signals. The number of the synchro and stuffing bits in the high-rate signal and intermediate-rate signals being known, only the low-rate signals are stuffed in dependence upon the difference between their own timing and the local timing at the multiplexing station. Blank intervals are provided in the low-rate signals having the duration of the synchro and stuffing bits in the intermediate-rate signals divided by the intermediate-to-low rate ratio and blank intervals are provided in the intermediate-rate signals having the duration of the synchro and stuffing bits in the high-rate signal divided by the high-to-intermediate rate ratio. Synchro and stuffing bits are inserted in the intervals resulting from the bit per bit multiplexing of the blank intervals.
Inventors
- 👤 Frederic M. Platet
- 👤 Yvon N. Madec
- 👤 Patrick E. Boutmy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 13:13
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/07; H04J3/073
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
409 words
A digital multiplexing and demultiplexing system in which a number of incoming asynchronous low rate component signals can be time multiplexed into an outgoing single high rate signal by way of locally formed synchronous intermediate rate signals, the intermediate rate being a first multiple of the low rate and the high rate being a second multiple of the intermediate rate, the low rate signals comprising information bits and the intermediate rate signals and the high rate signal comprising information bits, frame locking bits, stuffing indication bits and stuffing bits arranged in frames, the system comprising: a. means for stuffing the incoming asynchronous low rate signals in dependance upon the difference between their own originating timing frequencies and a local predetermined timing frequency slightly higher than all said originating timing frequencies; b. means for providing in each of said low rate signals a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the intermediate rate signals divided by said first multiple; c. means for inserting, in said low rate signal component blank bit slots, bits of selected value; d. a first stage for multiplexing the low rate stuffed signals having blank bit slots therein and bits of selected value inserted in said slots into the intermediate rate signals whereby the information bits of the low rate stuffed signals are multiplexed into the information bits of said intermediate rate signals and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the intermediate rate signals; e. means for providing in each of said intermediate rate signals a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the high rate signal divided by said second multiple; f. means for inserting, in said intermediate rate signals component blank bit slots, bits of selected value; and g. a second stage for multiplexing the intermediate rate signals having blank bit slots therein and bits of selected values inserted in said slots into the high rate signal whereby the information bits of the intermediate rate signals are multiplexed into the information bits of said high rate signal and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the high rate signal.
Claim 2
Dependent Claim
409 words
A digital multiplexing and demultiplexing system in which a number of incoming asynchronous low rate component signals can be time multiplexed into an outgoing single high rate signal by way of locally formed synchronous intermediate rate signals, the intermediate rate being a first multiple of the low rate and the high rate being a second multiple of the intermediate rate, the low rate signals comprising information bits and the intermediate rate signals and the high rate signal comprising information bits, frame locking bits, stuffing indication bits and stuffing bits arranged in frames, the system comprising: a. means for stuffing the incoming asynchronous low rate signals in dependance upon the difference between their own originating timing frequencies and a local predetermined timing frequency slightly higher than all said originating timing frequencies; b. means for providing in each of said low rate signals a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the intermediate rate signals divided by said first multiple; c. means for inserting, in said low rate signal component blank bit slots, bits of selected value; d. a first stage for multiplexing the low rate stuffed signals having blank bit slots therein and bits of selected value inserted in said slots into the intermediate rate signals whereby the information bits of the low rate stuffed signals are multiplexed into the information bits of said intermediate rate signals and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the intermediate rate signals; e. means for providing in each of said intermediate rate signals a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the high rate signal divided by said second multiple; f. means for inserting, in said intermediate rate signals component blank bit slots, bits of selected value; and g. a second stage for multiplexing the intermediate rate signals having blank bit slots therein and bits of selected values inserted in said slots into the high rate signal whereby the information bits of the intermediate rate signals are multiplexed into the information bits of said high rate signal and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the high rate signal.
Claim 3
Dependent Claim
531 words
A digital multiplexing and demultiplexing system in which a number of incoming asynchronous low rate component signals can be time multiplexed into an outgoing single high rate signal by way of locally formed synchronous intermediate rate signals, the intermediate rate being a first multiple of the low rate and the high rate being a second multiple of the intermediate rate, the low rate signals comprising information bits and the intermediate rate signals and the high rate signal comprising information bits, frame locking bits, stuffing indication bits and stuffing bits arranged in bits slots and in frames, the system comprising: a. means for stuffing the incoming asynchronous low rate signals in dependance upon the difference between their own originating timing frequencies and a local predetermined timing frequency slightly higher than all said originating timing frequencies; b. first means for defining addresses of the bit slots of the intermediate rate signals containing said frame locking bits, stuffing indication bits and stuffing bits and means, controlled by said first address defining means, for scanning synchronously said low rate signals and said intermediate rate signals; c. means for providing in the parts of said low rates signals scanned synchronously with the frame locking, stuffing indication and stuffing bits a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the intermediate rate signals divided by said first multiple; d. means for inserting, in said low rate signal component blank bit slots, bits of selected value; e. a first stage for multiplexing the low rate stuffed signals having blank bit slots therein and bits of selected value inserted in said slots into the intermediate rate signals whereby the information bits of the low rate stuffed signals are multiplexed into the information bits of said intermediate rate signals and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the intermediate rate signals; f. second means for defining addresses of the bit slots of the high rate signals containing said frame locking bits, stuffing indication bits and stuffing bits and means, controlled by said second address defining means, for scanning synchronously said intermediate rate signals and said high rate signal; g. means for providing in the parts of said intermediate rate signals scanned synchronously with the frame locking, stuffing indication and stuffing bits a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the high rate signal divided by said second multiple; h. means for inserting, in said intermediate rate signals component blank bit slots, bits of selected value; and i. a second stage for multiplexing the intermediate rate signals having blank bit slots therein and bits of selected values inserted in said slots into the high rate signal whereby the information bits of the intermediate rate signals are multiplexed into the information bits of said high rate signal and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the high rate signal.
Claim 4
Dependent Claim
531 words
A digital multiplexing and demultiplexing system in which a number of incoming asynchronous low rate component signals can be time multiplexed into an outgoing single high rate signal by way of locally formed synchronous intermediate rate signals, the intermediate rate being a first multiple of the low rate and the high rate being a second multiple of the intermediate rate, the low rate signals comprising information bits and the intermediate rate signals and the high rate signal comprising information bits, frame locking bits, stuffing indication bits and stuffing bits arranged in bits slots and in frames, the system comprising: a. means for stuffing the incoming asynchronous low rate signals in dependance upon the difference between their own originating timing frequencies and a local predetermined timing frequency slightly higher than all said originating timing frequencies; b. first means for defining addresses of the bit slots of the intermediate rate signals containing said frame locking bits, stuffing indication bits and stuffing bits and means, controlled by said first address defining means, for scanning synchronously said low rate signals and said intermediate rate signals; c. means for providing in the parts of said low rates signals scanned synchronously with the frame locking, stuffing indication and stuffing bits a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the intermediate rate signals divided by said first multiple; d. means for inserting, in said low rate signal component blank bit slots, bits of selected value; e. a first stage for multiplexing the low rate stuffed signals having blank bit slots therein and bits of selected value inserted in said slots into the intermediate rate signals whereby the information bits of the low rate stuffed signals are multiplexed into the information bits of said intermediate rate signals and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the intermediate rate signals; f. second means for defining addresses of the bit slots of the high rate signals containing said frame locking bits, stuffing indication bits and stuffing bits and means, controlled by said second address defining means, for scanning synchronously said intermediate rate signals and said high rate signal; g. means for providing in the parts of said intermediate rate signals scanned synchronously with the frame locking, stuffing indication and stuffing bits a number of component blank bit slots equal to the number of the frame locking, stuffing indication and stuffing bits in the frame of the high rate signal divided by said second multiple; h. means for inserting, in said intermediate rate signals component blank bit slots, bits of selected value; and i. a second stage for multiplexing the intermediate rate signals having blank bit slots therein and bits of selected values inserted in said slots into the high rate signal whereby the information bits of the intermediate rate signals are multiplexed into the information bits of said high rate signal and the blank bit slots having bits of selected value inserted therein are multiplexed into the frame locking, stuffing indication and stuffing bits of the high rate signal.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-10-19 | 1980-04-19 | 1980-10-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-10-19 | 1984-04-19 | 1984-10-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-10-19 | 1988-04-19 | 1988-10-19 | $7700.00 | Window Closed / Lapsed |