Asynchronous time division multiplexer and demultiplexer

Claim 2

An asynchronous pulse code modulation multiplexer and demultiplexer combination to multiplex n asynchronous data groups having a first bit rate into a synchronous data stream having a predetermined fixed data format and a second bit rate greater than said first bit rate and to demultiplex said data groups from said data stream, where n is greater than one, comprising: n inputs, each of said inputs being provided for a different one of said data groups; n first means, each of said first means being coupled to a different one of said inputs, certain ones of said first means generating a stuff request signal upon achieving a predetermined phase difference between said first and second bit rates; second means coupled in common to each of said first means, said second means responding to said stuff request signal from each of said first means to produce a stuff control signal for each of said certain ones of said first means and to multiplex unstuffed and stuffed data groups received from said first means according to said data format; each of said certain ones of said first means responding to an associated one of said stuff control signals to produce only a single stuff bit for each of said stuff request signal for addition to the associated one of said certain ones of said data groups at a given bit position within said data format to produce stuffed data groups for multiplexing with unstuffed data groups by said second means to provide said synchronous data stream; third means coupled to said second means to transmit said data stream along a given propagation medium; fourth means coupled to said propagation medium to receive said data stream; fifth means coupled to said fourth means, said fifth means being synchronized to said data stream to produce a destuff control signal upon occurrence of each of said stuff bits; and n sixth means coupled to said fifth means, each of said sixth means responding to an associated one of said destuff control signals to delete said stuff bit from said certain ones of said data groups, each of said sixth means providing an associated one of said data groups at the output thereof.

Claim 3

A combination according to claim 1, wherein each of said first means includes an elastic store having seventh means coupled to an associated one of said n inputs responsive to an associated one of said data groups and to a first reference signal having a third bit rate less than sAid first bit rate to generate a write clock having said third bit rate, eighth means coupled to said second means responsive to a second reference signal having said second bit rate to generate a read clock having said second bit rate, a storage means coupled to said associated one of said n inputs, said seventh means and said eighth means responsive to said write clock to load said storage means with bits of said associated one of said data groups and to said read clock to unload said storage means, and a phase comparator coupled to said seventh means and said eighth means to produce said stuff request signal during the time position of said data format allocated to said associated one of said data group when there is a predetermined phase difference between said write and read clocks, said eighth means responding to said stuff control signal to inhibit said read clock one bit period resulting in the last bit of said associated one of said data group being read out of said storage means twice to provide said single stuff bit and thus a stuffed data group for coupling to said second means for multiplexing into said data stream.

Claim 4

A combination according to claim 2, wherein said seventh means includes a positive transition generator coupled to said associated one of said n inputs responsive to said associated one of said data groups to provide a first given output signal, a binary divide-by-two means coupled to the output of said generator to divide said first given output signal by two, an EXCLUSIVE-OR gate coupled to the output of said divide-by-two means responsive to said first given output signal divided by two and said first reference to provide a second given output signal, and a binary divide-by-eight means coupled to the output of said gate and an input of said generator providing a third given output signal which is a multiple of said write clock.

Claim 5

A combination according to claim 1, wherein each of said sixth means includes an elastic store having a storage means coupled to said fith means, seventh means coupled to said fifth means and said storage means responsive to a first reference signal having said second bit rate to generate a write clock to control the loading of said storage means with an associated one of said stuffed data groups demultiplexed from said data stream, and eighth means coupled to said seventh means and said storage means responsive to a second reference signal having a third bit rate less than said first bit rate to generate a read clock to unload said storage means to provide said associated one of said data groups as the demultiplexed output of an associated one of said sixth means, said seventh means being responsive to said destuff control signal to inhibit said write clock to prevent said stuff bit from being loaded into said storage means and thereby deleting said stuff bit from said associated one of said stuffed data groups.

Claim 6

A combination according to claim 4, wherein said eighth means includes a phase locked loop having a phase comparator responsive to said write and read clocks to produce a phase control signal, a low pass filter coupled to said phase comparator to pass said phase control signal therethrough, a voltage controlled oscillator coupled to said filter responsive to said phase control signal to adjust the frequency of the output signal of said oscillator, a frequency adder coupled to said oscillator to add the frequencies of said output signal of said oscillator and said second reference signal, and a binary divider coupled to the output of said adder to provide said read clock.

Claim 7

A combination according to claim 1, wherein each of said first means includes a first elastic store having seventh means coupled to an associated one of said n inputs responsive to an associated one of said data groups and to a first reference signal having a third bit rate less than said first bit rate to generate a wrIte clock having said third bit rate, eighth means coupled to said second means responsive to a second reference signal having said second bit rate to generate a read clock having said second bit rate, a first storage means coupled to said associated one of said n inputs, said seventh means and said eighth means responsive to said write clock to load said first storage means with bits of said associated one of said data groups and to said read clock to unload said first storage means, and a phase comparator coupled to said seventh means and said eighth means to produce said stuff request signal during the time position of said data format allocated to said associated one of said data group when there is a predetermined phase difference between said write and read clocks, said eighth means responding to said stuff control signal to inhibit said read clock one bit period resulting in the last bit of said associated one of said data group being read out of said first storage means twice to provide said single stuff bit and thus a stuffed data group for coupling to said second means for multiplexing into said data stream; and each of said sixth means includes a second elastic store having a second storage means coupled to said fifth means, ninth means coupled to said fifth means and said second storage means responsive to a first reference signal having said second bit rate to generate a write clock to control the loading of said second storage means with an associated one of said stuffed data groups demultiplexed from said data stream, and tenth means coupled to said ninth means and said second storage means responsive to a second reference signal having a third bit rate less than said first bit rate to generate a read clock to unload said second storage means to provide said associated one of said data groups as the demultiplexed output of an associated one of said sixth means, said ninth means being responsive to said destuff control signal to inhibit said write clock to prevent said stuff bit from being loaded into said second storage means and thereby deleting said stuff bit from said associated one of said stuffed data groups.

Claim 8

A combination according to claim 6, wherein said tenth means includes a phase locked loop having a phase comparator responsive to said write and read clocks to produce a phase control signal, a low pass filter coupled to said phase comparator to pass said phase control signal therethrough, a voltage controlled oscillator coupled to said filter responsive to said phase control signal to adjust the frequency of the output signal of said oscillator, a frequency adder coupled to said oscillator to add the frequencies of said output signal of said oscillator and said second reference signal, and a binary divider coupled to the output of said adder to provide said read clock.

Claim 9

A combination according to claim 6, wherein said seventh means includes a positive transition generator coupled to said associated one of said n inputs responsive to said associated one of said data groups to provide a first given output signal, a binary divide-by-two means coupled to the output of said generator to divide said first given output signal by two, an EXCLUSIVE-OR gate coupled to the output of said divide-by-two means responsive to said first given output signal divided by two and said first reference to provide a second given output signal, and a binary divide-by-eight means coupled to the output of said gate and an input of said generator providing a third given output signal which is a multiple of said write clock.

Claim 10

A combination according to claim 1, wherein said data format includes 64 midframes within a single superframe, and 15 subframes within each of said midframes, the odd numbered ones of said subframes in each of said midframes including nine bits and the even numbered one of said subframes in each of said midframes Including eight bits, the first eight bits of each of said subframes in each of said midframes conveying data groups and the ninth bit of said odd numbered ones of said subframes in each of said midframes being employed as bits of an overhead channel, said overhead channel in each of said midframes including three digital voice orderwire bits, one control and signalling bit, two short sync bits to define a short sync code, one digital data bit and one long sync bit providing one bit of a long sync code; and said second means includes a first source of reference signal having said second bit rates, a first binary divider and decoding logic means coupled to said first source to produce a fast group select code, subframe timing signals and overhead channel timing signals to define said subframes and the bits of said overhead channel, a second binary divider and decoding logic means coupled in series with said first divider and logic means to produce midframe timing signals to define said midframes and to produce said short sync code, a third binary divider and decoding logic means coupled in series with said second divider and logic means to produce a slow group select code, superframe timing signals to define said superframe and to produce a pseudo-random long sync code, a stuff control circuit coupled to each of said first means and said first, second and third divider and logic means responsive to said subframe timing signals, said fast group select code, said midframe timing signals, said slow group select code, said superframe timing signals and said stuff request signals to produce said stuff control signal and a control code for each of said stuff request signals conveyed by one bit of said overhead channel in a plurality of said midframes, a first multiplexer coupled to said third divider and logic means and said stuff control circuit to multiplex said control codes, digital data orderwire signalling, and digital voice orderwire signalling to form a control channel, a second multiplexer coupled to said second and third divider and logic means and said first multiplexer to multiplex said control channel, digital data orderwire signal, digital voice orderwire signal and said control channel to form said overhead channel, and a third multiplexer coupled to each of said first means, said source, said first divider and logic means and said second multiplexer to multiplex said overhead channel and said stuffed and unstuffed data groups to form said data stream.

Claim 11

A combination according to claim 9, wherein said stuff control circuit includes a second source of sampling timing signals, a third source of halt timing signals, a code comparator coupled to said first divider and logic means and said third divider and logic means responsive to said fast group select code and said slow group select code to produce a combined timing signal, a first AND gate coupled to said second source and said comparator to produce in response to said sampling timing signals and said combined timing signal a sampling pulse, a sampling flip flop coupled in common to each of said first means and said first AND gate responsive to said stuff request signals and said sampling pulse to produce said control code for each of said stuff request signals, and a second AND gate coupled to said third source and said sampling flip flop responsive to each of said control codes and said halt timing to produce said stuff control signals for each of said stuff request signals.

Claim 12

A combination according to claim 1, wherein said data format includes 64 midframes within a single superframe, and 15 subframes within each of said midframes, the odd numbered ones of said subframes in each of said midframes including nine bits and the even numbered ones of said subframes in each of said midframes including eight bits, the first eight bits of each of said subframes in each of said midframes conveying data groupS and the ninth bit of said odd numbered ones of said subframes in each of said midframes being employed as bits of an overhead channel, said overhead channel in each of said midframes including three digital voice orderwire bits, one control and signalling bit, two short sync bits to define a short sync code, one digital data bit and one long sync bit providing one bit of a long sync code; and said fifth means includes clock recovery means coupled to said fourth means responsive to said received data stream to produce a clock having said second bit rate, a supergroup frame sync means coupled to said clock recovery means and said fourth means responsive to said clock, said short sync code and said long sync code to produce an inhibit signal when an out-of-sync condition is detected, first third coupled to said clock recovery means and said frame sync means responsive to said inhibit signal to inhibit a given number of bits of said clock to cooperate in establishing a frame sync condition, a first binary divider and decoding logic means coupled to said first inhibit logic to produce a fast group select code, subframe timing signals and overhead timing signals to define said subframes and the bits of said overhead channel, a second binary divider and decoding logic means coupled to said frame sync means to produce midframe timing signals to define said midframes and to produce said short sync code used as a reference short sync code by said frame sync means, second inhibit logic coupled in series between said first and second divider and logic means responsive to said inhibit signal to inhibit a given number of bits of the timing signal applied to the input of said second divider and logic means by said first divider and logic means to cooperate in establishing a frame sync condition, a third binary divider and decoding logic means coupled in series with said second divider and logic means and to said frame sync means to produce a slow group select code, superframe timing signals to define said superframe and to produce a pseudo-random long sync code used as a reference long sync code by said frame sync means, a first demultiplexer coupled to said fourth means, each of said sixth means and said first divider and logic means to demultiplex said stuffed and unstuffed data group and said overhead channel from said received data stream, a second demultiplexer coupled to said second and third divider and logic means and said first demultiplexer to demultiplex said control channel, digital data orderwire signal, and digital voice orderwire signal from said overhead channel, a third demultiplexer coupled to said third divider and logic means and said second demultiplexer to demultiplex said control codes, digital data orderwire signalling and digital voice orderwire signalling from said control channel, and a destuff control circuit coupled to each of said sixth means and said first, second and third divider and logic means responsive to said control codes, said subframe timing signals, said fast group select code, said midframe timing signals, said slow group select code and said superframe timing signals to produce a destuff control signal for each of said stuff bits whose time position in said data format is indicated by said control codes.

Claim 13

A combination according to claim 1, wherein said data format includes 64 midframes within a single superframe, and 15 subframes within each of said midframes, the odd numbered ones of said subframes in each of said midframes including nine bits and the even numbered ones of said subframes in each of said midframes including eight bits, the first eight bits of each of said subframes in each of said midframes conveying data groups and the ninth bit of said odd numbered ones of said subframes in each of said midframes being employed as bits of an overhead channel, said overhead channel in each of said midframes including three digital voice orderwire bits, one control and signalling bit, two short sync bits to define a short sync code, one digital data bit and one long sync bit providing one bit of a long sync code; said second means includes a first source of reference signal having said second bit rate, a first binary divider and decoding logic means coupled to said first source to produce a fast group select code, subframe timing signals and overhead channel timing signals to define said subframes and the bits of said overhead channel, a second binary divider and decoding logic means coupled in series with said first divider and logic means to produce midframe timing signals to define said midframes and to produce said short sync code, a third binary divider and decoding logic means coupled in series with said second divider and logic means to produce a slow group select code, superframe timing signals to define said superframe and to produce a pseudo-random long sync code, a stuff control circuit coupled to each of said first means and said first, second and third divider and logic means responsive to said subframe timing signals, said fast group select code, said midframe timing signals, said slow group select code, said superframe timing signals and said stuff request signals to produce a said stuff control signal and a control code for each of said stuff request signals conveyed by one bit of said overhead channel in a plurality of said midframes, a first multiplexer coupled to said third divider and logic means and said stuff control circuit to multiplex said control codes, digital data orderwire signalling, and digital voice orderwire signalling to form a control channel, a second multiplexer coupled to said second and third divider and logic means and said first multiplexer to multiplex said control channel, digital data orderwire signal, digital voice orderwire signal and said control channel to form said overhead channel, and a third multiplexer coupled to each of said first means, said source, said first divider and logic means and said second multiplexer to multiplex said overhead channel and said stuffed and unstuffed data group to form said data stream; and said fifth means includes clock recovery means coupled to said fourth means responsive to said received data stream to produce a clock having said second bit rate, a supergroup frame sync means coupled to said clock recovery means and said fourth means responsive to said clock, said short sync code and said long sync code to produce an inhibit signal when an out-of-sync condition is detected, first inhibit logic coupled to said clock recovery means and said frame sync means responsive to said inhibit signal to inhibit a given number of bits of said clock to cooperate in establishing a frame sync condition, a fourth binary divider and decoding logic means coupled to said first inhibit logic to produce a fast group select code, subframe timing signals and overhead timing signals to define said subframes and the bits of said overhead channel, a fifth binary divider and decoding logic means coupled to said frame sync means to produce midframe timing signals to define said midframes and to produce said short sync code used as a reference short sync code by said frame sync means, second inhibit logic coupled in series between said fourth and fifth divider and logic means responsive to said inhibit signal to inhibit a given number of bits of the timing signal applied to the input of said fifth divider and logic means by said fourth divider and logic means to cooperate in establishing a frame sync condition, a sixth binary divider and decoding logic means coupled in series with said fifth divider and logic means and to said frame sync means to produce a slow group select code, superframe timing signals to define said superframe and to produce a pseudo-random long sync code used as a reference long sync code by said frame sync means, a first demultiplexer coupled to said fourth Means, each of said sixth means and said fourth divider and logic means to demultiplex said stuffed and unstuffed data group and said overhead channel from said received data stream, a second demultiplexer coupled to said fifth and sixth divider and logic means and said first demultiplexer to demultiplex said control channel, digital data orderwire signal, and digital voice orderwire signal from said overhead channel, a third demultiplexer coupled to said sixth divider and logic means and said second demultiplexer to demultiplex said control codes, digital data orderwire signalling and digital voice orderwire signalling from said control channel, and a destuff control circuit coupled to each of said sixth means and said fourth, fifth and sixth divider and logic means responsive to said control codes, said subframe timing signals, said fast group select code, said midframe timing signals, said slow group select code and said superframe timing signals to produce a destuff control signal for each of said stuff bits whose time position in said data format is indicated by said control codes.

Claim 14

A combination according to claim 12, wherein said stuff control circuit includes a second source of sampling timing signals, a third source of halt timing signals, a code comparator coupled to said first divider and logic means and said third divider and logic means responsive to said fast group select code and said slow group select code to produce a combined timing signal, a first AND gate coupled to said second source and said comparator to produce in response to said sampling timing signals and said combined timing signal a sampling pulse, a sampling flip flop coupled in common to each of said first means and said first AND gate responsive to said stuff request signals and said sampling pulse to produce said control code for each of said stuff request signals, and a second AND gate coupled to said third source and said sampling flip flop responsive to each of said control codes and said halt timing signal to produce said stuff control signals for each of said stuff request signals.

Claim 15

An asynchronous pulse code modulation multiplexer to multiplex n asynchronous data groups having a first bit rate into a synchronous data stream having a predetermined fixed data format and a second bit rate greater than said first bit rate where n is an integer greater than one, comprising: n inputs, each of said inputs being provided for a different one of said data groups; n first means, each of said first means being coupled to a different one of said inputs, certain ones of said first means generating a stuff request signal upon achieving a predetermined phase difference between said first and second bit rates; and second means coupled in common to each of said first means, said second means responding to said stuff request signal from each of said certain ones of said first means to produce a stuff control signal for each of said certain ones of said first means and to multiplex unstuffed and stuffed data groups received from said first means according to said data format; each of said certain ones of said first means responding to an associated one of said stuff control signals to produce only a single stuff bit for each of said stuff request signal for addition to the associated one of said certain ones of said data groups at a given bit position within said data format to produce stuffed data groups for multiplexing with unstuffed data groups by said second means to provide said synchronous data stream.

Claim 16

An asynchronous pulse code modulation multiplexer to multiplex n asynchronous data groups having a first bit rate into a synchronous data stream having a predetermined fixed data format and a second bit rate greater than said first bit rate where n is an integer greater than one, comprising: n inputs, each of said inputs being provided for a different one of said data groups; n first means, each of said first means being coupled to a different one of said inputs, certain ones of said first means generating a stuff request signal upon achieving a predetermined phase difference between said first and second bit rates; and second means coupled in common to each of said first means, said second means responding to said stuff request signal from each of said certain ones of said first means to produce a stuff control signal for each of said certain ones of said first means and to multiplex unstuffed and stuffed data groups received from said first means according to said data format; each of said certain ones of said first means responding to an associated one of said stuff control signals to produce only a single stuff bit for each of said stuff request signal for addition to the associated one of said certain ones of said data groups at a given bit position within said data format to produce stuffed data groups for multiplexing with unstuffed data groups by said second means to provide said synchronous data stream.

Claim 17

A multiplexer according to claim 14, wherein each of said first means includes an elastic store having seventh means coupled to an associated one of said n inputs responsive to an associated one of said data groups and to a first reference signal having a third bit rate less than said first bit rate to generate a write clock having said third bit rate, eighth means coupled to said second means responsive to a second reference signal having said second bit rate to generate a read clock having said second bit rate, a storage means coupled to said associated one of said n inputs, said seventh means and said eighth means responsive to said write clock to load said storage means with bits of said associated one of said data groups and to said read clock to unload said storage means, and a phase comparator coupled to said seventh means and said eighth means to produce said stuff request signal during the time position of said data format allocated to said associated one of said data group when there is a predetermined phase difference between said write and read clocks, said eighth means responding to said stuff control signal to inhibit said read clock one bit period resulting in the last bit of said associated one of said data group being read out of said storage means twice to provide said single stuff bit and thus a stuffed data group for coupling to said second means for multiplexing into said data stream.

Claim 18

A multiplexer according to claim 15, wherein said seventh means includes a positive transition generator coupled to said associated one of said n inputs responsive to said associated one of said data groups to provide a first given output signal, a binary divide-by-two means coupled to the output of said generator to divide said first given output signal by two, an EXCLUSIVE-OR gate coupled to the output of said divide-by-two means responsive to said first given output signal divided by two and said first reference to provide a second given output signal, and a binary divide-by-eight means coupled to the output of said gate and an input of said generator providing a third given output signal which is a multiple of said write clock.

Claim 19

A multiplexer according to claim 14, wherein said data format includes 64 midframes within a single superframe, and 15 subframes within each of said midframes, the odd numbered ones of said subframes in each of said midframes including nine bits and the even numbered ones of said subframes in each of said midframes including eight bits, the first eight bits of each of said subframes in each of said midframes conveying data groups and the ninth bit of said odd numbered ones of said subframes in each of said midframes being employed as bits of an overhead channel, said overhead channel in each of said midframes including three digital voice orderwire bits, one control and signalling bit, two short sync bits to define a short sync code, one digital data bit and one long sync bit providing one bit of a long sync code; and said second means includes a first source of reference signal having said second bit rate, a first binary divider and decoding logic means coupled to said first source to produce a fast group select code, subframe timing signals and overhead channel timing signals to define said subframes and the bits of said overhead channel, a second binary divider and decoding logic means coupled in series with said first divider and logic means to produce midframe timing signals to define said midframes and to produce said short sync code, a third binary divider and decoding logic means coupled in series with said second divider and logic means to produce a slow group select code, superframe timing signals to define said superframe and to produce a pseudo-random long sync code, a stuff control circuit coupled to each of said first means and said first, second and third divider and logic means responsive to said subframe timing signals, said fast group select code, said midframe timing signals, said slow group select code, said superframe timing signals and said stuff request signals to produce said stuff control signal and a control code for each of said stuff request signals conveyed by one bit of said overhead channel in a plurality of said midframes, a first multiplexer coupled to said third divider and logic means and sAid stuff control circuit to multiplex said control codes, digital data orderwire signalling, and digital voice orderwire signalling to form a control channel, a second multiplexer coupled to said second and third divider and logic means and said first multiplexer to multiplex said control channel, digital data orderwire signal, digital voice orderwire signal and said control channel to form said overhead channel, and a third multiplexer coupled to each of said first means, said source, said first divider and logic means and said second multiplexer to multiplex said overhead channel and said stuffed and unstuffed data groups to form said data stream.

Claim 20

A multiplexer according to claim 17, wherein said stuff control circuit includes a second source of sampling timing signals, a third source of halt timing signals, a code comparator coupled to said first divider and logic means and said third divider and logic means responsive to said fast group select code and said slow group select code to produce a combined timing signal, a first AND gate coupled to said second source and said comparator to produce in response to said sampling timing signals and said combined timing signal a sampling pulse, a sampling flip flop coupled in common to each of said first means and said first AND gate responsive to said stuff request signals and said sampling pulse to produce said control code for each of said stuff request signals, and a second AND gate coupled to said third source and said sampling flip flop responsive to each of said control codes and said halt timing signal to produce said stuff control signals for each of said stuff request signals.

Claim 21

An asynchronous pulse code modulation demultiplexer to demultiplex a synchronous data stream having a predetermined fixed data format and a first bit rate into n asynchronous data groups having a second bit rate less than said first bit rate, said data groups being made synchronous with said data stream by adding only one stuff bit to certain ones of said data groups at different/given bit positions within said data format, where n is an integer greater than one, comprising: an input for said data stream; first means coupled to said input, said first means being synchronized to said data stream to produce a destuff control signal upon occurrence of each of said stuff bits; and n second means coupled to said first means, each of said second means responding to an associated one of said destuff control signal to delete said stuff bit from said certain ones of said data groups, each of said second means providing an associated one of said data groups at the output thereof.

Claim 22

An asynchronous pulse code modulation demultiplexer to demultiplex a synchronous data stream having a predetermined fixed data format and a first bit rate into n asynchronous data groups having a second bit rate less than said first bit rate, said data groups being made synchronous with said data stream by adding only one stuff bit to certain ones of said data groups at different/given bit positions within said data format, where n is an integer greater than one, comprising: an input for said data stream; first means coupled to said input, said first means being synchronized to said data stream to produce a destuff control signal upon occurrence of each of said stuff bits; and n second means coupled to said first means, each of said second means responding to an associated one of said destuff control signal to delete said stuff bit from said certain ones of said data groups, each of said second means providing an associated one of said data groups at the output thereof.

Claim 23

A demultiplexer according to claim 19, wherein each of said second means includes an elastic store having a storage means coupled to said fifth means, seventh means coupled to said fifth means and said storage means responsive to a first reference signal having said second bit rate to generate a write clock to control the loading of said storage means with an associated one of said stuffed data groups demultiplexed from said data stream, and eighth means coupled to said seventh means and said storage means responsive to a second reference signal having a third bit rate less than said first bit rate to generate a read clock to unload said storage means to provide said associated one of said data groups as the demultiplexed output of an associated one of said sixth means, said seventh means being responsive to said destuff control signal to inhibit said write clock to prevent said stuff bit from being loaded into said storage means and thereby deleting said stuff bit from said associated one of said stuffed data groups.

Claim 24

A demuliplexer according to claim 20, wherein said eighth means includes a phase locked loop having a phase comparator responsive to said write and read clocks to produce a phase control signal, a low pass filter coupled to said phase Comparator to pass said phase control signal therethrough, a voltage controlled oscillator coupled to said filter responsive to said phase control signal to adjust the frequency of the output signal of said oscillator, a frequency adder coupled to said oscillator to add the frequencies of said output signal of said oscillator and said second reference signal, and a binary divider coupled to the output of said adder to provide said read clock.

Claim 25

A demultiplexer according to claim 19, wherein said data format includes 64 midframes within a single superframe, and 15 subframes within each of said midframes, the odd numbered ones of said subframes in each of said midframes including nine bits and the even numbered ones of said subframes in each of said midframes including eight bits, the first eight bits of each of said subframes in each of said midframes conveying data groups and the ninth bit of said odd numbered ones of said subframes in each of said midframes being employed as bits of an overhead channel, said overhead channel in each of said midframes including three digital voice orderwire bits, one control and signalling bit, two short sync bits to define a short sync code, one digital data bit and one long sync bit providing one bit of a long sync code; and said first means includes clock recovery means coupled to said input responsive to said received data stream to produce a clock having said second bit rate, a supergroup frame sync means coupled to said clock recovery means and said input responsive to said clock, said short sync code and said long sync code to produce an inhibit signal when an out-of-sync condition is detected, first inhibit logic coupled to said clock recovery means and said frame sync means responsive to said inhibit signal to inhibit a given number of bits of said clock to cooperate in establishing a frame sync condition, a first binary divider and decoding logic means coupled to said first inhibit logic to produce a fast group select code, subframe timing signals and overhead timing signals to define said subframes and the bits of said overhead channel, a second binary divider and decoding logic means coupled to said frame sync means to produce midframe timing signals to define said midframes and to produce said short sync code used as a reference short sync code by said frame sync means, second inhibit logic coupled in series between said first and second divider and logic means responsive to said inhibit signal to inhibit a given number of bits of the timing signal applied to the input of said second divider and logic means by said first divider and logic means to cooperate in establishing a frame sync condition, a third binary divider and decoding logic means coupled in series with said second divider and logic means and to said frame sync means to produce a slow group select code, superframe timing signals to define said superframe and to produce a pseudo-random long sync code used as a reference long sync code by said frame sync means, a first demultiplexer coupled to said input, each of said sixth means and said first divider and logic means to demultiplex said stuffed and unstuffed data group and said overhead channel from said received data stream, a second demultiplexer coupled to said second and third divider and logic means and said first demultiplexer to demultiplex said control channel, digital data orderwire signal, and digital voice orderwire signal from said overhead channel, a third demultiplexer coupled to said third divider and logic means and said second demultiplexer to demultiplex said control codes, digital data orderwire signalling and digital voice orderwire signalling from said control channel, and a destuff control circuit coupled to each of said sixth means and said first, second and third divider and logic means responsive to said control codes, said subframe timing signals, said fast group select code, said midframE timing signals, said slow group select code and said superframe timing signals to produce a destuff control signal for each of said stuff bits whose time position in said data format is indicated by said control codes.