Mosfet integrated delay line for digital signals

Claim 1

A MOSFET integrated delay line for digital signals comprising stages of inverters connected in series with respect to the signal flow, characterized in that: each inverter in said stages is a conventional type of CMOS inverter formed by the series connection of the controlled current paths of an N-channel transistor and of a P- channel transistor: toward each CMOS inverter there is connected on the side of the N-channel transistor an N-channel constant-current transistor and, on the side of the P-channel transistor a P-channel constant-current transistor in series to the respective pole of the source of supply voltage; all of the N-channel constant-current transistors form part of an N-channel multiple current mirror; all of the P-channel constant-current transistors form part of a P-channel multiple current mirror; and all transistors of the N-channel multiple current mirror and the P-channel multiple current mirror are so dimensioned as to be capable of conducting currents which are equal in terms of magnitude and equal in relation to an adjustable reference current.