Delay circuit for gate-array LSI

Claim 2

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND) ; a plurality of P-channel transistors (Q l p to Q 4 p) connected in series between said first power supply means and said output terminal; and a plurality of N-channel transistors (Q ln to Q 4n ) connected in series between said output terminal and said second power means; operable to be said P -channel transistors / se q uen- tially turned on from the outside to the inside by a fall of potential at said input terminal and to be sequentially turned off from the inside to the outside by a rise of potential at said input terminal; operable to be said N-channel transistors/ sequentially turned on from the outside to the inside by a rise of - potential at said input terminal and to be sequentially turned off from the inside to the outside by a fall of potential at said input terminal.

Claim 3

A delay circuit comprising: an input terminal (IN); point an intermediate terminal /(C) ; an output terminal (OUT); first and second power supply means (V cc , GND) ; a first inverter (INVA) linked between point said input terminal and said intermediate terminal, said first inverter comprising: a plurality of first P-channel transistors (Q l p to Q 4p ) connected in series between said first power supply means and said intermediate terminal point, said first operable to be P-channel transistors operable to be driven by a potential at said input terminal; a plurality of first N-channel transistors (Q 1n to Q4n) connected in poin series between said intermediate terminal point and said second power supply terminal, said first N-channel transistors operable to be driven by a potential at said input terminal; and a second inverter (INVB) linked between said intermediate terminal/and said output terminal, said second inverter comprising: a plurality of second P-channel transistors (Q l p' to Q 4 p') connected in series between said first power supply means and said output terminal, said second P-channe transistors operable to be driven by a potential at said intermediate terminal point, and a plurality of second N-channel transistors (Q 1n ' to Q 4n ') connected in series between said output terminal and said second power supply terminal, said second N -channel transistors operable to be driven by a potential at said intermediate terminals point.

Claim 4

A delay circuit comprising: an input terminal (IN); point an intermediate terminal /(C) ; an output terminal (OUT); first and second power supply means (V cc , GND) ; a first inverter (INVA) linked between point said input terminal and said intermediate terminal, said first inverter comprising: a plurality of first P-channel transistors (Q l p to Q 4p ) connected in series between said first power supply means and said intermediate terminal point, said first operable to be P-channel transistors operable to be driven by a potential at said input terminal; a plurality of first N-channel transistors (Q 1n to Q4n) connected in poin series between said intermediate terminal point and said second power supply terminal, said first N-channel transistors operable to be driven by a potential at said input terminal; and a second inverter (INVB) linked between said intermediate terminal/and said output terminal, said second inverter comprising: a plurality of second P-channel transistors (Q l p' to Q 4 p') connected in series between said first power supply means and said output terminal, said second P-channe transistors operable to be driven by a potential at said intermediate terminal point, and a plurality of second N-channel transistors (Q 1n ' to Q 4n ') connected in series between said output terminal and said second power supply terminal, said second N -channel transistors operable to be driven by a potential at said intermediate terminals point.

Claim 5

A circuit as set forth in claim 2, further comprising: a third inverter (INVA') linked between said first and second inverters, said third inverter comprising a pair of P-channel/N-channel transistors connected in series, and a fourth inverter (INVB') connected to the output of said second inverter, said fourth inverter comprising a pair of P-channel/N-channel transistors connected in series.

Claim 6

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) connected in series between said input terminal and said output terminal, each of said first and second inverters comprising a number of P -channel transistors and an equal number of /N-channel transistors connected in series between said first and second power supply terminals; common outputs of pairs of P-channel/N-channel transistors of said second inverter being fed back to inputs of pairs of P-channel/N-channel transistors of said first inverter.

Claim 7

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) connected in series between said input terminal and said output terminal, each of said first and second inverters comprising a number of P -channel transistors and an equal number of /N-channel transistors connected in series between said first and second power supply terminals; common outputs of pairs of P-channel/N-channel transistors of said second inverter being fed back to inputs of pairs of P-channel/N-channel transistors of said first inverter.

Claim 8

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each comprising a number of P-channel transistors and an equal number of /N-channel transistors connected in series between said first and second power supply means; an outermost pair of P-channel/N-channel transistors of said first inverter operable to be driven by a potential at said input terminal; pairs of P-channel/N-channel tran- sistors of said second inverter operable to be sequentially driven from the outside to the inside by common outputs of pairs of P-channel/N-channel transistors of said first inverter; the pairs of P-channel/N-channel transistors of said first inverter, except for the outermost operable to be pair, each/ sequentially driven by a common output of respective a/ pair of P-channel/N-channel transistors of said second inverter; the common output of an innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.

Claim 9

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each comprising a number of P-channel transistors and an equal number of /N-channel transistors connected in series between said first and second power supply means; an outermost pair of P-channel/N-channel transistors of said first inverter operable to be driven by a potential at said input terminal; pairs of P-channel/N-channel tran- sistors of said second inverter operable to be sequentially driven from the outside to the inside by common outputs of pairs of P-channel/N-channel transistors of said first inverter; the pairs of P-channel/N-channel transistors of said first inverter, except for the outermost operable to be pair, each/ sequentially driven by a common output of respective a/ pair of P-channel/N-channel transistors of said second inverter; the common output of an innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.

Claim 10

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) an equal number of each having a number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; an outermost pair of P-channel/N-channel operable to be transistors of said first inverter driven by the potential at said input terminal; an outermost pair of P-channel/N-channel operable to be transistors of said second inverter / driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; inside pairs of P-channel/N-channel operable to be transistors of said first inverter / driven by the common output of the outermost pair of P-channel/N-channel transistors of said second inverter; inside pairs of P-channel/N-channel operable to be transistors of said second inverter / driven by the common output of an innermost pair of P-channel/N-channel transistors of said first inverter; the output of an innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.

Claim 11

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) an equal number of each having a number of P-channel transistors and N-channel transistors connected in series between said first and second power supply means; an outermost pair of P-channel/N-channel operable to be transistors of said first inverter driven by the potential at said input terminal; an outermost pair of P-channel/N-channel operable to be transistors of said second inverter / driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; inside pairs of P-channel/N-channel operable to be transistors of said first inverter / driven by the common output of the outermost pair of P-channel/N-channel transistors of said second inverter; inside pairs of P-channel/N-channel operable to be transistors of said second inverter / driven by the common output of an innermost pair of P-channel/N-channel transistors of said first inverter; the output of an innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.

Claim 12

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having a number of P-channel transistors and an equal number of /N-channel transistors connected in series between said first and second power supply means; an outermost pair of P-channel/N-channel operable to be transistors of said first inverter / driven by the potential at said input terminal; an outermost pair of P-channel/N-channel operable to be transistors of said second inverter / driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; inside pairs of P-channel/N-channel transistors of said first inverter operable to be driven by the common output of an innermost pair of P-channel/N-channel transistors of said second inverter; inside pairs of P-channel/N-channel transistors of said second inverter operable to be driven by the common output of an innermost pair of P-channel/N-channel transistors of said first inverter; the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.

Claim 13

A delay circuit comprising: an input terminal (IN); an output terminal (OUT); first and second power supply means (V cc , GND); and first and second inverters (INVA, INVB) each having a number of P-channel transistors and an equal number of /N-channel transistors connected in series between said first and second power supply means; an outermost pair of P-channel/N-channel operable to be transistors of said first inverter / driven by the potential at said input terminal; an outermost pair of P-channel/N-channel operable to be transistors of said second inverter / driven by the common output of the outermost pair of P-channel/N-channel transistors of said first inverter; inside pairs of P-channel/N-channel transistors of said first inverter operable to be driven by the common output of an innermost pair of P-channel/N-channel transistors of said second inverter; inside pairs of P-channel/N-channel transistors of said second inverter operable to be driven by the common output of an innermost pair of P-channel/N-channel transistors of said first inverter; the output of the innermost pair of P-channel/N-channel transistors of said second inverter being connected to said output terminal.