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US4805173A
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Error control method and apparatus
Assignee: Thinking Machines Corp
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Filing: 1986-12-10
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Granted: 1989-02-14
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Expires: 2006-12-10
Abstract
Abstract A method and apparatus are described for error control and correction which operates across multiple processors and multiple computer memories. In accordance with the invention, data signals from a plurality of processors are applied in parallel to a syndrome generator that generates a syndrome related to such signals. The syndrome is then stored in parallel in a plurality of read/write memories at the same address as the data signals from which the syndrome was generated. When the data signals are read from memory, they are again provided to the syndrome generator which again generates a new syndrome. At the same time the old syndrome signals stored at the same memory addresses are read from memory and compared with the new syndrome. If the two syndromes are the same, there is no error and the data signals are valid. If the syndromes are different, a syndrome decoder determines if sufficient information is available in the syndrome signals to correct the error and does so if it can.
Inventors
- 👤 W. Daniel Hillis
- 👤 Brewster Kahle
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 21:36
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1004; G06F11/1008; G06F11/1048
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
171 words
Error detection circuitry for use in a parallel processor comprising: a plurality of processors and at least one read/write memory, a plurality of inputs equal in number to the number of processors, each input being connected to a different processor, means for providing signals in parallel from the plurality of processors to said inputs, means for generating a syndrome from said parallel signals on said inputs, such that the syndrome is generated from signals from more than one processor, means for storing in parallel in said memory said parallel signals and said syndrome generated therefrom, such that a syndrome generated from signals from more than one processor is associated in said memory with said signals from more than one processor, means for reading from said memory said parallel signals and the syndrome associated therewith, means for generating a new syndrome from said parallel signals read from memory, and means for comparing the syndrome read from said parallel memory with the new syndrome generated from the parallel signals read from said memory.
Claim 2
Dependent Claim
171 words
Error detection circuitry for use in a parallel processor comprising: a plurality of processors and at least one read/write memory, a plurality of inputs equal in number to the number of processors, each input being connected to a different processor, means for providing signals in parallel from the plurality of processors to said inputs, means for generating a syndrome from said parallel signals on said inputs, such that the syndrome is generated from signals from more than one processor, means for storing in parallel in said memory said parallel signals and said syndrome generated therefrom, such that a syndrome generated from signals from more than one processor is associated in said memory with said signals from more than one processor, means for reading from said memory said parallel signals and the syndrome associated therewith, means for generating a new syndrome from said parallel signals read from memory, and means for comparing the syndrome read from said parallel memory with the new syndrome generated from the parallel signals read from said memory.
Claim 3
Dependent Claim
32 words
The apparatus of claim 1 further comprising means for determining from the syndrome read from memory and the new syndrome generated if an error detected by said comparing means can be corrected.
Claim 4
Dependent Claim
17 words
The apparatus of claim 2 further comprising means for correcting an error detected by said comparing means.
Claim 5
Dependent Claim
15 words
The apparatus of claim 1 wherein signals from different processors are stored in different memories.
Claim 6
Independent Claim
156 words
A method of detecting errors in a parallel processor comprising the steps of: providing signals from a plurality of processors in parallel to a plurality of inputs equal in number to the number of processors, such that each signal is provided to a different input, generating a syndrome from said parallel signals on said inputs, such that the syndrome is generated from signals from more than one processor, storing in parallel in at least one read/write memory said parallel signals and said syndrome generated therefrom, such that a syndrome generated from signals from more than one processor is associated in said memory with said signals from more than one processor, reading from said memory said parallel signals and the syndrome associated therewith, generating a new syndrome from the parallel signals read from the memory, and comparing the syndrome read from said parallel memory with a new syndrome generated from the parallel signals read from said memory.
Claim 7
Independent Claim
156 words
A method of detecting errors in a parallel processor comprising the steps of: providing signals from a plurality of processors in parallel to a plurality of inputs equal in number to the number of processors, such that each signal is provided to a different input, generating a syndrome from said parallel signals on said inputs, such that the syndrome is generated from signals from more than one processor, storing in parallel in at least one read/write memory said parallel signals and said syndrome generated therefrom, such that a syndrome generated from signals from more than one processor is associated in said memory with said signals from more than one processor, reading from said memory said parallel signals and the syndrome associated therewith, generating a new syndrome from the parallel signals read from the memory, and comparing the syndrome read from said parallel memory with a new syndrome generated from the parallel signals read from said memory.
Claim 8
Dependent Claim
22 words
The method of claim 5 further comprising the step of determining if an error detected in said comparing step can be corrected.
Claim 9
Dependent Claim
18 words
The method of claim 6 further comprising the step of correcting an error detected in said comparing step.
Claim 10
Dependent Claim
15 words
The method of claim 5 wherein signals from different processors are stored in different memories.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-02-14 | 1992-08-15 | 1993-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-02-14 | 1996-08-15 | 1997-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-02-14 | 2000-08-15 | 2001-02-14 | $7700.00 | Window Closed / Lapsed |